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參數資料
| 型號： | TS8308500VGL |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, CBGA68 |
| 封裝： | 11 X 11 MM, 1.27MM PITCH, CERAMIC, BGA-68 |
| 文件頁數： | 19/50頁 |
| 文件大?。?/td> | 491K |
| 代理商： | TS8308500VGL |
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26
TS8308500
2193A–BDC–04/03
No performance degradation (i.e.: due to timing jitter) is observed in this particular single-
ended configuration up to 500 Msps Nyquist Conditions (F
IN = 250 MHz).
This is all the more so since the inverted phase clock input pin is 50
terminated on the pack-
age (that is very close to one of the neighboring shield ground pins, which constitutes the local
ground reference for the inphase clock input).
Thus the TS8308500 differential clock input buffer will fully reject the local ground noise (and
any capacitively and inductively coupled noise) as common mode effects. Moreover, a very
low phase noise sinewave generator must be used for enhanced jitter performance.
The typical in-phase clock input amplitude is 1V, centered on 0V (ground) common mode. This
corresponds to a typical clock input power level of 4 dBm into the 50
termination resistor. Do
not exceed 10 dBm to avoid saturation of the preamplifier input transistors.
Figure 30. Single-ended Clock Input (Ground Common Mode):
VCLK common mode = 0V; VCLKB = 0V; 4 dBm typical clock input power level (into 50
termination resistor)
Note:
Do not exceed 10 dBm into the 50
termination resistor for the single clock input power level.
Differential ECL Clock
Input
The clock inputs can be driven differentially with nominal -0.8V/-1.8V ECL levels.
In this mode, a low-phase noise sinewave generator can be used to drive the clock inputs, fol-
lowed by a power splitter (hybrid junction) in order to obtain 180
° out of phase sinewave
signals. Biasing tees can be used for offseting the common mode voltage to ECL levels.
Note: As the biasing tees propagation times are not matching, a tunable delay line is required
in order to ensure the signals are 180
° out of phase, especially at fast clock rates in the
500 Msps range.
Figure 31. Differential Clock Inputs (ECL Levels)
50
(on package)
1 M
0.4 pF
-0.5V
+0.5V
t
[V]
VCLK
CLK or CLKB double pad (pins 37, 38 or 39, 40)
CLK or CLKB
50
reverse termination
VCLK = 0V
VCLK
50
(on package)
1 M
0.4 pF
CLK or CLKB double pad (pins 37, 38 or 39, 40)
CLK or CLKB
-2V
50
reverse termination
-1.8V
-0.8V
[mV]
VCLK
t
VCLKB
Common mode = -1.3V
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