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參數(shù)資料
型號(hào)： TS8388BCFS9NC1ZB9
廠商： E2V TECHNOLOGIES PLC
元件分類： ADC
英文描述： 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
封裝： CERAMIC, QFP-68
文件頁(yè)數(shù)： 22/43頁(yè)
文件大小： 825K
代理商： TS8388BCFS9NC1ZB9
TS8388BFS
29/42
Preliminary Beta Site
7.3.
ANALOG INPUTS (VIN) (VINB)
The analog input Full Scale range is 0.5 Volts peak to peak (Vpp), or -2 dBm into the 50 ohms termination resistor.
In differential mode input configuration, that means 0.25 Volt on each input, or +/- 125 mV around zero volt. The input common mode is
GROUND.
The typical input capacitance is 3 pF for TS8388BFS in CQFP package.
The input capacitance is mainly due to the package.(note : the ESD protections are not connected(but present) on the inputs.
Differential inputs voltage span
-125
125
[mV]
-250 mV
250 mV
VIN
500mV
Full Scale
analog input
t
VINB
(VIN,VINB) = +/- 250 mV = 500 mV diff
0 Volt
Differential versus single ended analog input operation
The TS8388BFS can operate at full speed in either differential or single ended configuration.
This is explained by the fact the ADC uses a high input impedance differential preamplifier stage, (preceeding the Sample and hold stage),
which has been designed in order to be entered either in differential mode or single–ended mode.
This is true so long as the out of phase analog input pin VINB is 50 ohms terminated very closely to one of the neighboring shield ground pins
(52, 53, 58, 59) which constitute the local ground reference for the inphase analog input pin (VIN).
Thus the differential analog input preamplifier will fully reject the local ground noise ( and any capacitively and inductively coupled noise) as
common mode effects.
In typical single–ended configuration, enter on the (VIN) input pin, with the inverted phase input pin (VINB) grounded through the 50 ohms
termination resistor.
In single–ended input configuration, the in-phase input amplitude is 0.5 Volt peak to peak,centered on 0V. (or -2 dBm into 50 ohms.)
The inverted phase input is at ground potential through the 50 ohms termination resistor.
However, dynamic performances can be somewhat improved by entering either analog or clock inputs in differential mode.
Typical Single ended analog input configuration
VIN or VINB
VIN or VINB double pad (pins 54, 55 or 56, 57)
50
(external)
50
reverse termination
1M
3 pF
-250
250
[mV]
500 mV
Full Scale
analog input
t
VINB
VIN
VINB = 0V
V
IN
= +/- 250 mV
500 mV diff
相關(guān)PDF資料
PDF描述
TS8388BCFS9QC3ZB9 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68
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