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參數資料
| 型號： | TS8388BMFB/T |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數： | 31/62頁 |
| 文件大?。?/td> | 1267K |
| 代理商： | TS8388BMFB/T |
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37
0860E–BDC–05/07
e2v semiconductors SAS 2007
TS8388B
Figure 8-10. Differential Output: 50
Terminated
Figure 8-11. Differential Output: Open Loaded
8.7
Out of Range Bit
An Out of Range (OR, ORB) bit is provided that goes to logical high state when the input exceeds the
positive full scale or falls below the negative full scale.
When the analog input exceeds the positive full scale, the digital output data remain at high logical state,
with (OR, ORB) at logical one.
When the analog input falls below the negative full scale, the digital outputs remain at logical low state,
with (OR, ORB) at logical one again.
8.8
Gray or Binary Output Data Format Select
The TS8388B internal regeneration latches indecision (for inputs very close to latches threshold) may
produce errors in the logic encoding circuitry and leading to large amplitude output errors.
This is due to the fact that the latches are regenerating the internal analog residues into logical states
with a finite voltage gain value (Av) within a given positive amount of time
(t):
Av = exp(
(t)/τ), with τ the positive feedback regeneration time constant.
1.6V
75
75
-
+
11 mA
DVEE
50
50
impedance
Out
OutB
50
50
1.38V/1.05V
10 nF
Differential output:
+0.33V = 0.660V
1.05V/1.38V
Common mode level: -1.2V
(-1.2V below VPLUSD level)
VPLUSD = 2.4V
1.6V
75
75
-
+
11 mA
DVEE
75
75
impedance
Out
OutB
1.6V/0.8V
Differential output:
+0.8V = 1.6V
0.8V/1.6V
Common mode level: -1.2V
(-1.2V below VPLUSD level)
VPLUSD = 2.4V
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相關代理商/技術參數 |
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|---|---|
| TS8388BMFS | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
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