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參數(shù)資料
| 型號(hào)： | TS8388BMFS9QB3ZB9 |
| 廠商： | ATMEL CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數(shù)： | 40/43頁 |
| 文件大小： | 825K |
| 代理商： | TS8388BMFS9QB3ZB9 |
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TS8388BFS
6
/42
Preliminary Beta Site
Parameter
Symb
Temp
Test
level
Min
Typ
Max
Unit
DIGITAL OUTPUTS (notes 1,6)
Single ended or differential input mode, 50 % clock duty cycle (CLK,CLKB), Binary output data format,
Tj (typical) = 70
°C. Full temperature range :-55°C < Tc ; Tj < +125°C.
Logic compatibility for digital outputs
( Depending on the value of VPLUSD )
(see Application Notes)
ECL or LVDS
Differential output voltage swings ( assuming VPLUSD = 0V) :
75
open transmission lines ( ECL levels )
75
differentially terminated
50
differentially terminated
Full
IV
1.50
0.70
0.54
1.620
0.825
0.660
V
Output levels ( assuming VPLUSD = 0V)
75
open transmission lines
(note 6)
25
°C
IV
Logic “0” voltage
VOL
-1.62
-1.54
V
Logic “1” voltage
VOH
-0.88
-0.8
V
Output levels ( assuming VPLUSD = 0V)
75
differentially terminated
(note 6)
25
°C
IV
Logic “0” voltage
VOL
-1.41
-1.34
V
Logic “1” voltage
VOH
-1.07
-1
V
Output levels ( assuming VPLUSD = 0V)
50
differentially terminated
(note 6)
25
°C
II
Logic “0” voltage
VOL
-1.35
-1.28
V
Logic “1” voltage
VOH
-1.09
-1.02
V
Output level drift with temperature
Full
IV
1.6
mV/
°C
DC ACCURACY
Single ended or differential input mode, 50 % clock duty cycle (CLK,CLKB), Binary output data format,
Tj (typical) = 70
°C. Full temperature range :-55°C < Tc ; Tj < +125°C.
Differential non linearity
(notes 2,3)
DNL
Full
I
VI
0.4
0.5
0.6
LSB
Integral non linearity
(notes 2,3)
INL
Full
I
VI
0.7
0.9
1
1.2
LSB
No missing codes
(note 3)
Full
Guaranteed over specified temperature range
Gain error
Full
I
VI
-10
-11
-2
6
7
% FS
Input offset voltage
Full
I
VI
-26
-30
-5
14
17
mV
Gain error drift
Offset error drift
Full
IV
100
40
125
50
150
60
ppm/
°C
ppm/
°C
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