- 您現在的位置：買賣IC網 > PDF目錄98300 > TS8388BMFSB/QQC1 (E2V TECHNOLOGIES PLC) 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 PDF資料下載
參數資料
| 型號： | TS8388BMFSB/QQC1 |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數： | 28/42頁 |
| 文件大小： | 1307K |
| 代理商： | TS8388BMFSB/QQC1 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當前第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
34
TS8388BFS
Product Specification
7.7.
OUT OF RANGE BIT
An Out of Range (OR,ORB) bit is provided that goes to logical high state when the input exceeds the positive full scale or falls below the
negative full scale.
When the analog input exceeds the positive full scale, the digital output datas remain at high logical state, with (OR,ORB) at logical one.
When the analog input falls below the negative full scale, the digital outputs remain at logical low state, with (OR,ORB) at logical one again.
7.8.
GRAY OR BINARY OUTPUT DATA FORMAT SELECT
The TS8388BFS internal regeneration latches indecision (for inputs very close to latches threshold) may produce errors in the logic encoding
circuitry and leading to large amplitude output errors.
This is due to the fact that the latches are regenerating the internal analog residues into logical states with a finite voltage gain value (Av) within
a given positive amount of time
(t) :
Av= exp(
(t)/τ) , with τ the positive feedback regeneration time constant.
The TS8388BFS has been designed for reducing the probability of occurence of such errors to approximately 10
-13 (targetted for the
TS8388BFS at 1GSPS).
A standard technique for reducing the amplitude of such errors down to +/-1 LSB consists to output the digital datas in Gray code format.
Though the TS8388BFS has been designed for featuring a Bit Error Rate of 10
-13 with a binary output format, it is possible for the user to select
between the Binary or Gray output data format, in order to reduce the amplitude of such errors when occuring, by storing Gray output codes.
Digital Datas format selection :
BINARY output format if GORB is floating or VCC.
GRAY output format if GORB is connected to ground (0V).
7.9.
DIODE PIN 49
One single pin is used for both DRRB input command and die junction monitoring. The pin denomination is DRRB/DIOD. Temperature
monitoring and Data Ready control by DRRB is not possible simultaneously.
-+
11 mA
DVEE
VPLUSD = 2.4V
75
75
50
50
impedance
10 nF
50
50
Out
1.38V / 1.05V
OutB
1.05V / 1.38V
Differential output :
± 0.33V = 0.660V
Common mode level : -1.2V
(-1.2V below VPLUSD level)
Figure 7 : DIFFERENTIAL OUTPUT : 50
TERMINATED
1.6V
-+
11 mA
DVEE
VPLUSD = 2.4V
75
75
75
75
impedance
Out
1.6V / 0.8V
OutB
0.8V / 1.6V
Differential output :
± 0.8V = 1.6V
Common mode level : -1.2V
(-1.2V below VPLUSD level)
Figure 8 : DIFFERENTIAL OUTPUT : OPEN LOADED
1.6V
相關PDF資料 |
PDF描述 |
|---|---|
| TS8388BMFSB/QNC1 | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS8388BMFSB/QQB2 | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS8388BMFSB/QNB3 | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS8388BMFSB/QQC2 | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| TS8388BMFSB/QQC2 | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TS8388BVF | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BVFS | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BVGL | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS8388BVGL (+LID) | 制造商:e2v technologies 功能描述:ADC 8-BIT 1 GSPS - Trays |
| TS83C194 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microcontroller |
發布緊急采購，3分鐘左右您將得到回復。