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參數(shù)資料
| 型號： | TS8388BVF |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數(shù)： | 21/44頁 |
| 文件大小： | 850K |
| 代理商： | TS8388BVF |
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TS8388BF
Preliminary Beta-Site
Specification
7.2.
PRINCIPLE OF DATA READY SIGNAL CONTROL BY DRRB INPUT COMMAND
7.2.1.
DATA READY OUTPUT SIGNAL RESET
The Data Ready signal is reset on falling edge of DRRB input command, on ECL logical low level (-1.8V). DRRB may also be tied to VEE = - 5V for
Data Ready output signal Master Reset. So long DRRB remains at logical low level, (or tied to VEE = - 5V), the Data Ready output remains at
logical zero and is independant of the external free running encoding clock.
The Data Ready output signal (DR,DRB) is reset to logical zero after TRDR= 920 ps typical.
TRDR is measured between the -1.3V point of the falling edge of DRRB input command and the zero crossing point of the differential Data Ready
output signal (DR,DRB).
The Data Ready Reset command may be a pulse of 1 ns minimum time width.
7.2.2.
DATA READY OUTPUT SIGNAL RESTART
The Data Ready output signal restarts on DRRB command rising edge, ECL logical high levels (-0.8V).
DRRB may also be Grounded, or is allowed to float, for normal free running Data Ready output signal.
The Data Ready signal restart sequence depends on the logical level of the external encoding clock, at DRRB rising edge instant :
1)
The DRRB rising edge occurs when external encoding clock input (CLK,CLKB) is LOW :
The Data Ready output first rising edge occurs after half a clock period on the clock falling edge, after a delay time TDR = 1320 ps already
defined hereabove.
2)
The DRRB rising edge occurs when external encoding clock input (CLK,CLKB) is HIGH :
The Data Ready output first rising edge occurs after one clock period on the clock falling edge, and a delay TDR = 1320ps.
Consequently, as the analog input is sampled on clock rising edge, the first digitized data corresponding to the first acquisition ( N ) after Data Ready
signal restart ( rising edge ) is always strobed by the third rising edge of the data ready signal.
The time delay (TD1) is specified between the last point of a change in the differential output data (zero crossing point) to the rising or falling edge of
the differential Data Ready signal (DR,DRB) (zero crossing point).
Note 1 : For normal initialization of Data Ready output signal, the external encoding clock signal frequency and level must be controlled.
It is reminded that the minimum encoding clock sampling rate for the ADC is 10 MSPS and consequently the clock cannot be stopped.
Note 2 : One single pin is used for both DRRB input command and die junction temperature monitoring.
Pin denomination will be DRRB/DIOD.( On former version denomination was DIOD. )
Temperature monitoring and Data Ready control by DRRB is not possible simultaneously.
7.3.
ANALOG INPUTS (VIN) (VINB)
The analog input Full Scale range is 0.5 Volts peak to peak (Vpp), or -2 dBm into the 50 ohms termination resistor.
In differential mode input configuration, that means 0.25 Volt on each input, or +/- 125 mV around zero volt. The input common mode is GROUND.
The typical input capacitance is 3 pF for TS8388B in CQFP package.
The input capacitance is mainly due to the package.(note : the ESD protections are not connected(but present) on the inputs.
Differential inputs voltage span
-125
125
[mV]
-250 mV
250 mV
VIN
500mV
Full Scale
analog input
t
VINB
(VIN,VINB) = +/- 250 mV = 500 mV diff
0 Volt
Differential versus single ended analog input operation
The TS8388BF can operate at full speed in either differential or single ended configuration.
This is explained by the fact the ADC uses a high input impedance differential preamplifier stage, (preceeding the Sample and hold stage), which has
been designed in order to be entered either in differential mode or single–ended mode.
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