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參數資料
| 型號： | TS8388BVFS9QB2ZB9 |
| 廠商： | ATMEL CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP68 |
| 封裝： | CERAMIC, QFP-68 |
| 文件頁數： | 24/43頁 |
| 文件大小： | 825K |
| 代理商： | TS8388BVFS9QB2ZB9 |
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TS8388BFS
30
/42
Preliminary Beta Site
7.4.
CLOCK INPUTS (CLK) (CLKB)
The TS8388BFS can be clocked at full speed without noticeable performance degradation in either differential or single ended configuration.
This is explained by the fact the ADC uses a differential preamplifier stage for the clock buffer, which has been designed in order to be entered
either in differential or single–ended mode.
7.4.1.
SINGLE ENDED CLOCK INPUT (GROUND COMMON MODE)
Although the clock inputs were intended to be driven differentially with nominal -0.8V / -1.8V ECL levels, the TS8388BFS clock buffer can
manage a single–ended sinewave clock signal centered around 0 Volt. This is the most convenient clock input configuration as it does not
require the use of a power splitter.
No performance degradation ( e.g. : due to timing jitter) is observed in this particular single–ended configuration up to 1.2GSPS Nyquist
conditions ( Fin = 600 MHz ).
This is true so long as the inverted phase clock input pin is 50 ohms terminated very closely to one of the neighbouring shield ground pin, which
constitutes the local Ground reference for the inphase clock input.
Thus the TS8388BFS differential clock input buffer will fully reject the local ground noise ( and any capacitively and inductively coupled noise) as
common mode effects.
Moreover, a very low phase noise sinewave generator must be used for enhanced jitter performance.
The typical inphase clock input amplitude is 1 Volt peak to peak, centered on 0 Volt (ground) common mode.
This corresponds to a typical clock input power level of 4 dBm into the 50 ohms termination resistor.
Do not exceed 10 dBm to avoid saturation of the preamplifier input transistors.
The inverted phase clock input is grounded through the 50 ohms termination resistor.
Single ended Clock input (Ground common mode)
VCLK common mode = 0 Volt
VCLKB=0 Volt
4 dBm typical clock input power level
(into 50 ohms termination resistor)
[V]
t
VCLK
VCLKB = ( 0 V )
-0.5V
+0.5V
CLK or CLKB
50
(external)
50
reverse termination
1M
0.4 pF
CLK or CLKB double pad (pins 37, 38 or 39, 40)
Note 1 : Do not exceed 10 dBm into the 50 ohms termination resistor for single clock input power level.
7.4.2.
DIFFERENTIAL ECL CLOCK INPUT
The clock inputs can be driven differentially with nominal -0.8V / -1.8V ECL levels.
In this mode, a low phase noise sinewave generator can be used to drive the clock inputs, followed by a power splitter (hybrid junction) in order
to obtain 180 degrees out of phase sinewave signals. Biasing tees can be used for offseting the common mode voltage to ECL levels.
Note : As the biasing tees propagation times are not matching, a tunable delay line is required in order to ensure the signals to be 180 degrees
out of phase especially at fast clock rates in the GSPS range.
Differential Clock inputs (ECL Levels)
-0.8V
[mV]
t
-1.8V
VCLKB
VCLK
Common mode = -1.3 V
CLK or CLKB
50
reverse termination
1M
0.4 pF
-2V
50
(external)
CLK or CLKB double pad (pins 37, 38 or 39, 40)
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