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參數資料
| 型號： | TSA0801IF |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | 7 X 7 MM, PLASTIC, TQFP-48 |
| 文件頁數： | 5/21頁 |
| 文件大小： | 0K |
| 代理商： | TSA0801IF |
13/21
TSA0801 APPLICATION NOTE
NO
T
FOR
NEW
DESI
G
N
DETAILED INFORMATION
The TSA0801 is a High Speed analog to digital
converter based on a pipeline architecture and the
latest deep submicron CMOS process to achieve
the best performances in terms of linearity and
power consumption.
The pipeline structure consists of 9 internal con-
version stages in which the analog signal is fed
and sequentially converted into digital data.
Each 8 first stages consists of an Analog to Digital
converter, a Digital to Analog converter, a Sample
and Hold and a gain of 2 amplifier. A 1.5bit conver-
sion resolution is achieved in each stage. The lat-
est stage simply is a comparator. Each resulting
LSB-MSB couple is then time shifted to recover
from the conversion delay. Digital data correction
completes the processing by recovering from the
redundancy of the (LSB-MSB) couple for each
stage. The corrected data are outputted through
the digital buffers.
Signal input is sampled on the rising edge of the
clock while digital outputs are delivered on the fall-
ing edge of the Data Ready signal.
The advantages of such a converter reside in the
combination of pipeline architecture and the most
advanced technologies. The highest dynamic per-
formances are achieved while consumption re-
mains at the lowest level.
Some functionalities have been added in order to
simplify as much as possible the application
board. These operational modes are described in
the following table.
The TSA0801 is pin to pin compatible with the
10bits/25Msps
TSA1001,
the
10bits/50Msps
TSA1002 and the 12bits/50Msps TSA1201. This
ensures a conformity within the product family and
above all, an easy upgrade of the application.
OPERATIONAL MODES DESCRIPTION
Data Format Select (DFSB)
When set to low level (VIL), the digital input DFSB
provides a twoís complement digital output MSB.
This can be of interest when performing some fur-
ther signal processing.
When set to high level (VIH), DFSB provides a
standard binary output coding.
Output Enable (OEB)
When set to low level (VIL), all digital outputs
remain active and are in low impedance state.
When set to high level (VIH), all digital outputs
buffers are in high impedance state. This results in
lower consumption while the converter goes on
sampling.
When OEB is set to low level again, the data is
then valid on the output with a very short Ton
delay.
The timing diagram summarizes this operating
cycle.
Inputs
Outputs
Analog input differential level
DFSB
OEB
OR
DR
Most Significant Bit (MSB)
(VIN-VINB)
>
RANGE
H
L
H
CLK
D9
-RANGE
>
(VIN-VINB)
H
L
H
CLK
D9
RANGE> (VIN-VINB) >-RANGE
H
L
CLK
D9
(VIN-VINB)
>
RANGE
L
H
CLK
Complemented D9
-RANGE
>
(VIN-VINB)
L
H
CLK
Complemented D9
RANGE> (VIN-VINB) >-RANGE
L
CLK
Complemented D9
XX
H
HZ
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| TSA0801IFT | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| TSA1001IF | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TSA0801IFT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT, 40MSPS, 40mW A/D CONVERTER |
| TSA1 | 制造商:HellermannTyton 功能描述:66 block bridging clip |
| TSA10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EURO TERMINAL BLOCKS |
| TS-A10/15L | 制造商:Stellar labs (MCM Electronics) 功能描述:Toshiba Satellite Replacement Laptop Battery |
| TSA100008-1 | 制造商:Panasonic Industrial Company 功能描述:ANTENNA |
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