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參數資料
| 型號： | TSA0801IFT |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | ADC |
| 英文描述： | 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | 7 X 7 MM, PLASTIC, TQFP-48 |
| 文件頁數： | 9/21頁 |
| 文件大小： | 0K |
| 代理商： | TSA0801IFT |
TSA0801
17/21
NO
T
FOR
NEW
DESI
G
N
Dynamic characteristics, while not being as
remarkable as for differential configuration, are still
of very good quality.
Power consumption optimization
The internal architecture of the TSA0801 enables
to optimize the power consumption according to
the sampling frequency of the application. For this
purpose, a resistor is placed between IPOL and
the analog Ground pins.
The TSA0801 will combine highest performances
and lowest consumption at 40Msps when Rpol is
equal to 18k
.
At lower sampling frequency range (< 10Msps),
this value of resistor may be adjusted in order to
decrease
the
analog
current
without
any
degradation of dynamic performances.
As an example, 10mW total power consumption is
achieved at 5Msps with a Rpol value of 390k
.
The table below sums up the relevant data.
Total power consumption optimization
depending on Rpol value
Linearity, distortion performance towards Clock Duty Cycle variation
The TSA0801 has an outstanding behaviour towards clock duty cycle variation and it may be also
reinforced with adjustment of analog current consumption.
Linearity vs. Duty cycle
Fs=40MSPS; Icca=11mA; Fin=1MHz
Linearity vs. Duty cycle
Fs=40MSPS; consumption optimized; Fin=1MHz
Distortion vs. Duty cycle
Fs=40MSPS; Icca=11mA; Fin=1MHz
Distortion vs. Duty cycle
Fs=40MSPS; consumption optimized; Fin=1MHz
Fs (Msps)
5
15
25
40
Rpol (
k
)
390
40
25
18
Optimized
power (mW)
10
25
35
40
30
35
40
45
50
55
60
65
70
75
80
30
40
50
60
70
Duty Cycle (%)
Dynam
ic
par
a
m
e
te
rs
(
d
B)
5
5.5
6
6.5
7
7.5
8
E
N
O
B
(b
its
)
SINAD
SNR
ENOB
0
10
20
30
40
50
60
70
30
40
50
60
70
Duty Cycle (%)
Dy
na
m
ic
pa
ra
m
e
te
rs
(
d
B)
,
a
n
a
log
c
u
rre
nt
c
ons
.(
m
A)
5
5.5
6
6.5
7
7.5
8
E
N
O
B
(b
its
)
SINAD
SNR
ENOB
Icca (mA)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
30
40
50
60
70
Duty Cycle (%)
Dynam
ic
par
a
m
e
te
rs
(
d
B)
THD
SFDR
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
30
40
50
60
70
Duty Cycle (%)
Dy
na
m
ic
pa
ra
m
e
te
rs
(
d
B)
,
a
n
a
log
c
u
rre
nt
c
ons
.(
m
A)
0
10
20
30
40
50
60
70
80
90
100
a
n
a
log
c
u
rre
nt
c
ons
.(
m
A)
THD
SFDR
ICCA
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