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參數(shù)資料
| 型號： | TSA1002CF |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | 7 X 7 MM, PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 8/20頁 |
| 文件大小： | 236K |
| 代理商： | TSA1002CF |
Obsolete
Product(s)
- Obsolete
Product(s)
TSA1002
16/20
NO
T
FOR
NEW
DESI
G
N
Power consumption
The internal architecture of the TSA1002 enables
to optimize the power consumption according to
the sampling frequency of the application. For this
purpose, a resistor is placed between IPOL and
the analog Ground pins. The figure 10 sums up
the relevant data.
The TSA1002 will combine highest performances
and lowest consumption at 50Msps when Rpol is
in the range of 12k
to 20k.
At lower sampling frequency, this value of resistor
may be changed and the consumption will
decrease as well.
Figure 10 : Analog Current consumption vs. Fs
According value of Rpol polarization resistance
Linearity, distortion performance towards
Clock Duty Cycle variation
The TSA1002 has an outstanding behaviour
towards clock duty cycle variation and it may be
also reinforced with adjustment of analog current
consumption.
Linearity vs. Duty cycle
Fs=50MSPS; consumption optimized; Fin=1MHz
Distortion vs. Duty cycle
Fs=50MSPS; consumption optimized; Fin=1MHz
Linearity vs. Duty cycle
Fs=50MSPS; Icca=20mA; Fin=10MHz
Distortion vs. Duty cycle
Fs=50MSPS; Icca=20mA; Fin=10MHz
0
10
20
30
40
50
60
25
35
45
55
65
75
Fs (MHz)
Icca
(
m
A
)
0
2
4
6
8
10
12
14
16
18
20
Rpol
(
k
O
h
m
s
)
RPOL
ICCA
0
10
20
30
40
50
60
70
80
30
40
50
60
70
Duty Cycle (%)
Dy
na
m
ic
pa
ra
m
e
te
rs
(
d
B)
,
a
n
a
log
c
u
rre
nt
c
ons
.(
m
A)
3
4
5
6
7
8
9
10
E
N
O
B
(b
its
)
SINAD
ENOB
SNR
IccA
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
30
40
50
60
70
Duty Cycle (%)
D
y
n
a
mi
c
P
a
ra
me
te
rs
(
d
B
)
10
20
30
40
50
60
70
IccA
(
m
A
)
SFDR
THD
IccA
30
35
40
45
50
55
60
65
70
75
80
40
45
50
55
60
Duty Cycle (%)
Dynam
ic
par
a
m
e
te
rs
(
d
B)
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
10
E
N
O
B
(b
its
)
SINAD
ENOB
SNR
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
40
45
50
55
60
Duty Cycle (%)
D
y
n
a
mi
c
P
a
ra
me
te
rs
(
d
B
)
SFDR
THD
相關PDF資料 |
PDF描述 |
|---|---|
| TSA1002IF | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| TSA1002IFT | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| TSA1005-20IFT | 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| TSA1005-40IFT | 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| TSA1005I-40IF | 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TSA1002CFT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:10-BIT, 50MSPS, 50mW A/D CONVERTER |
| TSA1002IF | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:10-BIT, 50MSPS, 50mW A/D CONVERTER |
| TSA1002IFT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:10-BIT, 50MSPS, 50mW A/D CONVERTER |
| TSA1005 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DUAL-CHANNEL, 10-BIT, 20/40MSPS A/D CONVERTER |
| TSA1005-20IF | 制造商:STMicroelectronics 功能描述:ADC DUAL PIPELINED 20MSPS 10-BIT PARALLEL 48TQFP - Trays |
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