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參數資料
| 型號： | TSA1041IFT |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | ADC |
| 英文描述： | 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | 7 X 7 MM, TQFP-48 |
| 文件頁數： | 4/14頁 |
| 文件大小： | 287K |
| 代理商： | TSA1041IFT |
TSA1041
12/14
programming digit, pin SPEED as shown in Table
1:.
LVDS outputs:
The LVDS (Low-voltage differential signaling)
specifications of the TSA1041 are based on the
ANSI/TIA/EIA-644
LVDS
standard.
The
low
voltage swing (300mV) of LVDS reduces noise
generation. Moreover well-balanced and close
data transmission lines, such as twisted pairs
obtain the maximum common mode rejection.
A termination resistor of 100 ohms must be
added.
Layout precautions:
Grounding and bypassing:
To
obtain
the
best performances from the
TSA1041, a proper grounding and bypassing of
all
power
supplies
and
references
is
very
important. Bypass capacitors (470nF and 10nF
surface mounted capacitors) must be placed as
close as possible to the ADC pins in order to
improve high frequency bypassing and reduce
harmonic distortion (see figure 4). It will prevent
the high frequency transient current and noise
from
going
through
power
supplies
and
references lines.
It is recommended to use a four-layer PCB board
with top and bottom layers for signals, a ground
and a power layer. The use of multiple via to
connect power and ground traces to appropriate
planes will increase noise immunity.
Analog Channel matching:
The Differential analog input lines should be as
short as possible and be of equal lengths. The
length of each pair addressing the four A/D
converters should be very close. To minimize
crosstalk between channels, each analog pair
must respect a certain distance from other pair.
LVDS outputs and channels matching:
For these high data throughput (up to 500Mb/s),
the layout of LVDS traces must follow some rules:
- the differential impedance between the 2 traces
must be 100 ohms to avoid reflection. The surface
mounted termination resistor must be 100 ohms
(1%) as close as possible to the receiver inputs
- to avoid crosstalk, LVDS pairs should not be
placed too closed from each other.
- Same lengths between LVDS traces and as
short as possible (driver-receiver) to limit the skew
between channels and clocks.
- Isolation of LVDS lines with ground plane.
- Minimization of discontinuities on LVDS traces.
Fs (Msps)
SPEED
Pd (mW)
<40
1
380
40-50
0
440
Table 1 : : Programming for power
optimization versus speed
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