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參數(shù)資料
| 型號： | TSA1204IFT-E |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | ADC |
| 英文描述： | 2-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | 7 X 7 MM, PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 7/31頁 |
| 文件大小： | 435K |
| 代理商： | TSA1204IFT-E |
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TSA1204
Application information
15/31
8
Application information
The TSA1204 is a dual-channel, 12-bit resolution analog-to-digital converter based on a
pipeline structure and the latest deep submicron CMOS process to achieve the best
performance in terms of linearity and power consumption.
Each channel achieves 12-bit resolution through the pipeline structure which consists of 12
internal conversion stages in which the analog signal is fed and sequentially converted into
digital data. A latency time of 7 clock periods is necessary to obtain the digitized data on the
output bus.
The input signals are simultaneously sampled, for both channels, on the rising edge of the
clock. The output data is delivered on the rising edge of the clock for channel I and on the
falling edge of the clock for channel Q, as shown in Figure 2: Timing diagram on page 4. The
digital data produced at the different stages must be time delayed accordidng to the order of
conversion. Fianlly, a digital data correction completes the processing and ensures the
validity of the ending codes on the output bus.
The structure is specifically designed to accept differential signals only.
8.1
Additional functions
To simplify the application board as much as possible, the following operating modes are
provided:
●
Output enable mode (OEB)
●
Select mode (SELECT)
8.1.1
Output enable mode (OEB)
When set to low level (VIL), all digital outputs remain active and are in low impedance state.
When set to high level (VIH), all digital output buffers are in high impedance state while the
converter goes on sampling. When OEB is set to a low level again, the data arrives on the
output with a very short Ton delay. This mechanism allows the chip select of the device.
Figure 2: Timing diagram on page 4 summarizes this functionality.
If you do not want to use OEB mode, the OEB pin should be grounded through a low value
resistor.
8.1.2
Select mode (SELECT)
The digital data output from each of the ADC cores is multiplexed to share the same output
bus. This prevents an increase in the number of pins and allows to use the same package as
for a single-channel ADC like the TSA1201.
The information channel is selected with the "SELECT" pin. When set to high level (VIH),
channel I data is present on the D0-D11 output bus. When set to low level (VIL), channel Q
data is delivered on D0-D11.
By connecting SELECT to CLK, channel I and channel Q are simultaneously present on D0-
D11, channel I on the rising edge of the clock and channel Q on the falling edge of the clock.
(Refer to Figure 2: Timing diagram on page 4).
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