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參數資料
| 型號： | TSA5518M |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | 1.3 GHz bidirectional I2C-bus controlled synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO20 |
| 封裝： | 4.40 MM, PLASTIC, SOT-266-1, SSOP-20 |
| 文件頁數： | 6/20頁 |
| 文件大小： | 161K |
| 代理商： | TSA5518M |
1997 Mar 07
6
Philips Semiconductors
Product specification
1.3 GHz bidirectional I
2
C-bus controlled
synthesizer
TSA5518M
Read mode
The read data format is summarised in Table 5. Data can
be read out of the device by setting the R/W bit to logic 1.
After the slave address has been recognized, the device
generates an acknowledge pulse and the status word is
transferred on the SDA line (MSB first). Data is valid on the
SDA line during a HIGH of the SCL clock signal. A second
data byte can be read out of the device if the processor
generates an acknowledge on the SDA line. End of
transmission will occur if no acknowledge from the
processor occurs.The device will then release the data line
to allow the processor to generate a STOP condition.
When the port P6 is used as input, it must be programmed
in its high-impedance state. The POR flag (Power-on
reset) is set to logic 1 when V
CC
goes below 3 V and at
power-on. It is reset when an end of data is detected by the
device (end of a READ sequence). Control of the loop is
made possible with the in-lock flag FL which indicates
(FL = 1) when the loop is phase-locked. A built-in % level
A/D converter is available on I/O port P6. This converter
can be used to feed AFC information to the controller from
the IF section of the television as illustrated in the typical
application circuit in Fig.2. The relationship between bit
A2, A1 and A0 and the input voltage on port P6 is given in
Table 6.
Table 5
Read data format
Notes
1.
2.
3.
4.
5.
See Table 7.
POR: Power-on reset flag. (POR = 1 on power-on).
FL: in lock flag (FL = 1 when the loop is phase-locked).
A2, A1, A0: digital outputs of the 5 level A/D converter (see Table 6). Accuracy is
1
2
LSB. MSB is transmitted first.
Upon an acknowledge pulse from the controller, the device transfers the status byte again. If no acknowledge pulse
from the controller is received, data read is terminated.
BYTE
DESCRIPTION
MSB
LSB
ACKNOWLEDGE
1
2, ..
address
status byte(s)
1
1
0
0
0
0
0
0
MA1
(1)
A2
(4)
MA0
(1)
A1
(4)
1
LOW from device
note 5
POR
(2)
FL
(3)
A0
(4)
Table 6
Accuracy on the switching levels is
±
0.02V
CC
.
A/D converter levels
Table 7
Address selection
VOLTAGE APPLIED ON PIN P6
A2
A1
A0
0.6V
CC
to 5.5 V
0.45V
CC
to 0.6V
CC
0.3V
CC
to 0.45V
CC
0.15V
CC
to 0.3V
CC
0 to 0.15V
CC
1
0
0
0
0
0
1
1
0
0
0
1
0
1
0
VOLTAGE APPLIED ON PIN AS
MA1
MA0
0 to 0.1V
CC
always valid
0.4 to 0.6V
CC
0.9V
CC
to V
CC
0
0
1
1
0
1
0
1
Address selection
The module address contains programmable address bits
(MA1 and MA0) which offer the possibility of having
several synthesizers (up to 3) in one system by applying a
specific voltage on AS input. The relationship between
MA1 and MA0 and the input voltage on AS input is given
in Table 7.
Frequency lock flag (FL) definition
When the FL flag is logic 1, the maximum frequency
deviation dF from stable frequency can be expressed as:
K
K
O
C1
C2
with:
K
VCO
= oscillator slope (Hz/V)
I
CP
= charge pump current (A)
K
O
= 4
×
10
6
C1, C2 = loop filter capacitors.
df
-------------
±
I
CP
×
C1
C2
+
×
×
=
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