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參數資料
| 型號： | TSA5521 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 1.3 GHz universal bus-controlled TV synthesizer(1.3 GHz通用總線控制的TV合成器) |
| 中文描述： | 1.3 GHz的通用總線控制的電視頻率合成器（1.3千兆赫通用總線控制的電視合成器） |
| 文件頁數： | 6/24頁 |
| 文件大小： | 285K |
| 代理商： | TSA5521 |
1996 Oct 10
6
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizer
TSA5520; TSA5521
PINNING
SYMBOL
PIN
DESCRIPTION
RF
V
EE
V
CC1
V
CC2
BS4
BS3
BS2
BS1
CP
V
tune
SW
1
2
3
4
5
6
7
8
9
10
11
RF signal input
ground
supply voltage (+5 V)
band switch supply voltage (+12 V)
PNP band switch buffer output 4
PNP band switch buffer output 3
PNP band switch buffer output 2
PNP band switch buffer output 1
charge-pump output
tuning voltage output
bus format selection input, I
2
C-bus or
3-wire
lock detector output
serial clock input
serial data input/output
chip enable/address selection input
crystal oscillator input
LOCK
SCL
SDA
CE
XTAL
12
13
14
15
16
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
The device is controlled via the I
2
C-bus or the 3-wire bus
depending on the voltage applied to the SW input (pin 11).
A HIGH level on the SW input enables the 3-wire bus
inputs which are Chip Enable (CE), serial data input (SDA)
and serial clock input (SCL). A LOW level on the SW input
enables the I
2
C-bus inputs which are CE [Address
Selection (AS) input], serial data input/output (SDA) and
serial clock input (SCL). The bus format selection is given
in Table 2.
I
2
C-bus mode (SW = LOW);
see Table 3
Data bytes can be sent to the device after the address
transmission (first byte). Four data bytes are required to
fully program the device. The bus receiver has an
auto-increment facility which permits the programming of
the device within one single transmission
(address + 4 data bytes).
The device can also be partially programmed providing
that the first data byte following the address is Divider
Byte 1 (DB1) or the Control Byte (CB). The bits in the data
bytes are defined in Table 3.
The first bit of the first data byte transmitted indicates
whether frequency data (first bit = 0) or control and band
switch data (first bit = 1) will follow. Until an I
2
C-bus STOP
command is sent by the controller, additional data bytes
can be entered without the need to re-address the device.
The frequency register is loaded after the 8th clock pulse
of the second Divider Byte (DB2), the control register is
loaded after the 8th clock pulse of the Control Byte (CB)
and the band switch register is loaded after the 8th clock
pulse of the Band switch Byte (BB).
I
2
C-bus address selection
The module address contains programmable address bits
(MA1 and MA0) which offer the possibility of having
several synthesizers (up to 3) in one system by applying a
specific voltage to the CE input.
The relationship between MA1 and MA0 and the input
voltage applied to the CE input is given in Table 5.
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| TSA5521T | 1.3 GHz universal bus-controlled TV synthesizer |
| TSA5522 | 1.4 GHz I2C-bus controlled synthesizer |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TSA5521M | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.3 GHz universal bus-controlled TV synthesizer |
| TSA5521T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.3 GHz universal bus-controlled TV synthesizer |
| TSA5521TD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C-Bus Frequency Synthesizer |
| TSA5522 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.4 GHz I2C-bus controlled synthesizer |
| TSA5522M | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1.4 GHz I2C-bus controlled synthesizer |
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