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參數資料
| 型號： | TSA5527AT |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | 1.3 GHz universal bus-controlled TV synthesizers |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO16 |
| 封裝： | 3.90 MM, PLASTIC, SO-16 |
| 文件頁數： | 9/28頁 |
| 文件大?。?/td> | 290K |
| 代理商： | TSA5527AT |
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1996 Sep 24
9
Philips Semiconductors
Product specification
1.3 GHz universal bus-controlled
TV synthesizers
TSA5526; TSA5527
Table 9
ADC levels
Note
1.
Accuracy is
±
0.03V
CC1
.
3-wire bus mode (SW = open-circuit or V
CC1
);
see Figs 3
,
4 and 5
During a HIGH level on the CE input, the data is clocked
into the data register at the HIGH-to-LOW transition of the
clock pulse. The first four bits control the band switch
buffers and are loaded into the internal band switch
register on the 5th rising edge of the clock pulse.
The frequency bits are loaded into the frequency register
at the HIGH-to-LOW transition of the chip enable line when
an 18-bit or 19-bit data word is transmitted.
At power-on the charge-pump current is set to 280
μ
A, the
tuning voltage output is disabled (V
tune
= 33 V in
VOLTAGE APPLIED
AT ADC INPUT
(1)
A2
A1
A0
0.6V
CC1
to V
CC1
0.45V
CC1
to 0.6V
CC1
0.3V
CC1
to 0.45V
CC1
0.15V
CC1
to 0.3V
CC1
0 to 0.15V
CC1
1
0
0
0
0
0
1
1
0
0
0
1
0
1
0
application; see Fig.12), the test bits T2, T1 and T0 are set
to the 0 0 1 state in the normal mode with ACPS OFF for
TSA55226; TSA5527 and ACPS ON for TSA5526A;
TSA5527A. RSB is set to logic 1 (TSA5526) or logic 0
(TSA5527). When an 18-bit data word is transmitted, the
most significant bit of the divider N14 is internally set to
logic 0 and bit RSA is set to logic 1. When a 19-bit data
word is transmitted, bit RSA is set to logic 0.
When a 27-bit word is transmitted, the frequency bits are
loaded into the frequency register on the 20th rising edge
of the clock pulse and the control bits at the HIGH-to-LOW
transition of the chip enable line. In this mode, the
reference divider is given by the RSA and RSB bits
(see Table 7). The test bits T2, T1 and T0, the
charge-pump bit CP, the ratio select bit RSB and the
OS bit can only be selected or changed with a 27-bit
transmission. They remain programmed if an 18-bit or a
19-bit transmission occurs. Only RSA is controlled by the
transmission length when the 18-bit or 19-bit format is
used.
A data word of less than 18 bits will not affect the
frequency register of the device. The definition of the bits
is unchanged compared to the I
2
C-bus mode.
The power-on detection threshold voltage V
POR
is fixed to
V
CC1
= 2 V at room temperature. Below this threshold, the
device is reset to the power-on state previously described.
Fig.3 Normal mode; 18-bit data format (RSA = 1).
For TSA5526 bit RSB = logic 1 at power-on; the reference divider is 512 or 1024.
For TSA5527 bit RSB = logic 0 at power-on; the reference divider is 640.
For TSA5526 and TSA5527 the value of RSB can also be programmed by using the 27-bit data format. When returning to the normal mode, bit RSB
remains as programmed with the 27-bit data word.
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