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參數資料
| 型號： | TSC2003I |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 3-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | PLASTIC, TSSOP-16 |
| 文件頁數： | 15/20頁 |
| 文件大小： | 309K |
| 代理商： | TSC2003I |
TSC2003
4
SBAS162A
www.ti.com
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
POWER-SUPPLY REQUIREMENTS
+VDD
Specified Performance
2.7
3.6
V
Operating Range
2.5
5.25
V
Quiescent Current
Internal Reference OFF,
PD1 = PD0 = 0
High-Speed Mode: SCL = 3.4MHz
254
650
A
Fast Mode: SCL = 400kHz
95
A
Standard Mode: SCL = 100kHz
63
A
Internal Reference ON, PD0 = 0
1005
A
Power-Down Current when Part is
Internal Reference OFF,
Not Addressed
PD1 = PD0 = 0
High-Speed Mode: SCL = 3.4MHz
90
A
Fast Mode: SCL = 400kHz
21
A
Standard Mode: SCL = 100kHz
4
A
PD1 = PD0 = 0, SDA = SCL = +VDD
3
A
Power Dissipation
+VDD = +2.7V
1.8
mW
TEMPERATURE RANGE
Specified Performance
–40
+85
°C
NOTES: (1) LSB means Least Significant Bit. With VREF equal to +2.5V, one LSB is 610V. (2) Ensured by design, but not tested. Exceeding 50mA source current may
result in device degradation. (3) Difference between TEMP0 and TEMP1 measurement. No calibration necessary. (4) Temperature drift is –2.1mV/
°C.
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = –40°C to +85°C, +VDD = +2.7V, VREF = 2.5V external voltage, I2C bus frequency = 3.4MHz, 12-bit mode and digital inputs = GND or +VDD, unless
otherwise noted.
TSC2003E
TIMING CHARACTERISTICS
At TA = –40°C to +85°C, +VDD = +2.7V, unless otherwise noted. All values referred to VIHMIN and VILMAX levels.
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
SCL Clock Frequency
fSCL
Standard Mode
0
100
kHz
Fast Mode
0
400
kHz
High-Speed Mode, Cb = 100pF max
0
3.4
MHz
High-Speed Mode, Cb = 400pF max
0
1.7
MHz
Bus Free Time Between a STOP and
tBUF
Standard Mode
4.7
s
Start Condition
Fast Mode
1.3
s
Hold Time (Repeated) START
tHD; STA
Standard Mode
4.0
s
Condition
Fast Mode
600
ns
High-Speed Mode
160
ns
LOW Period of the SCL Clock
tLOW
Standard Mode
4.7
s
Fast Mode
1.3
s
High-Speed Mode, Cb = 100pF max
160
ns
High-Speed Mode, Cb = 400pF max
320
ns
HIGH Period of the SCL Clock
tHIGH
Standard Mode
4.0
s
Fast Mode
600
ns
High-Speed Mode, Cb = 100pF max
60
ns
High-Speed Mode, Cb = 400pF max
120
ns
Setup Time for a Repeated START
tSU; STA
Standard Mode
4.7
s
Condition
Fast Mode
600
ns
High-Speed Mode
160
ns
Data Setup Time
tSU; DAT
Standard Mode
250
ns
Fast Mode
100
ns
High-Speed Mode
10
ns
Data Hold Time
tHD; DAT
Standard Mode
0
3.45
s
Fast Mode
0
0.9
s
High-Speed Mode, Cb = 100pF max
0
70
ns
High-Speed Mode, Cb = 400pF max
0
150
ns
Rise Time of SCL Signal
trCL
Standard Mode
1000
ns
Fast Mode
20 + 0.1Cb
300
ns
High-Speed Mode, Cb = 100pF max
10
40
ns
High-Speed Mode, Cb = 400pF max
20
80
ns
Rise Time of SCL Signal After a
trCL1
Standard Mode
1000
ns
Repeated START Condition and
Fast Mode
20 + 0.1Cb
300
ns
After an Acknowledge Bit
High-Speed Mode, Cb = 100pF max
10
80
ns
High-Speed Mode, Cb = 400pF max
20
160
ns
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