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參數(shù)資料
型號: TSC2046IZQCR
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PBGA48
封裝: 4 X 4 MM, ROHS COMPLIANT, PLASTIC, VFBGA-48
文件頁數(shù): 9/33頁
文件大小: 774K
代理商: TSC2046IZQCR
TSC2046
SBAS265G OCTOBER 2002 REVISED JANUARY 2008
www.ti.com
17
16 Clocks-per-Conversion
The control bits for conversion n + 1 can be overlapped
with conversion n to allow for a conversion every 16 clock
cycles, as shown in Figure 11. This figure also shows
possible serial communication occurring with other serial
peripherals between each byte transfer from the processor
to the converter. This is possible, provided that each
conversion completes within 1.6ms of starting. Otherwise,
the signal that is captured on the input sample-and-hold
may droop enough to affect the conversion result. Note
that the TSC2046 is fully powered while other serial
communications are taking place during a conversion.
Digital Timing
Figure 9, Figure 12, and Table 6 provide detailed timing for
the digital interface of the TSC2046.
15 Clocks-per-Conversion
Figure 13 provides the fastest way to clock the TSC2046.
This method does not work with the serial interface of most
microcontrollers and digital signal processors, as they are
generally not capable of providing 15 clock cycles per
serial transfer. However, this method can be used with
field-programmable gate arrays (FPGAs) or application-
specific integrated circuits (ASICs). Note that this
effectively increases the maximum conversion rate of the
converter beyond the values given in the specification
tables, which assume 16 clock cycles per conversion.
1
DCLK
CS
81
11
DOUT
BUSY
S
DIN
Control Bits
S
Control Bits
10
98765
4
3
2
1
0
11 10
9
81
1
8
Figure 11.
Conversion Timing, 16 Clocks-per-Conversion, 8-Bit Bus Interface.
No DCLK delay required with dedicated serial port
PD0
t
BDV
t
DH
t
CH
t
CL
t
DS
t
CSS
t
DV
t
BD
t
BD
t
TR
t
BTR
t
DO
t
CSH
DCLK
CS
11
DOUT
BUSY
DIN
10
Figure 12. Detailed Timing Diagram
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