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參數(shù)資料
型號: TSC2100IRHBG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQCC32
封裝: 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù): 31/77頁
文件大小: 1079K
代理商: TSC2100IRHBG4
TSC2100
SLAS378 NOVEMBER 2003
www.ti.com
37
TSC2100 COMMUNICATION PROTOCOL
Register Programming
The TSC2100 is entirely controlled by registers. Reading and writing these registers is controlled by an SPI master and
accomplished by the use of a 16-bit command, which is sent prior to the data for that register. The command is constructed
as shown in Figure 34.
The command word begins with a R/W bit, which specifies the direction of data flow on the SPI serial bus. The following
4 bits specify the page of memory this command is directed to, as shown in Table 5. The next six bits specify the register
address on that page of memory to which the data is directed. The last five bits are reserved for future use and should be
written only with zeros.
Table 5. Page Addressing
PG3
PG2
PG1
PG0
PAGE ADDRESSED
0
1
0
1
0
2
0
1
Reserved
0
1
0
Reserved
0
1
0
1
Reserved
0
1
0
Reserved
0
1
Reserved
1
0
Reserved
1
0
1
Reserved
1
0
1
0
Reserved
1
0
1
Reserved
1
0
Reserved
1
0
1
Reserved
1
0
Reserved
1
Reserved
To read all the first page of memory, for example, the host processor must send the TSC2100 the command 0x8000 – this
specifies a read operation beginning at page 0, address 0. The processor can then start clocking data out of the TSC2100.
The TSC2100 automatically increments its address pointer to the end of the page; if the host processor continues clocking
data out past the end of a page, the TSC2100 sends back the value 0xFFFF.
Likewise, writing to page 1 of memory consists of the processor writing the command 0x0800, which specifies a write
operation, with PG0 set to 1, and all the ADDR bits set to 0. This results in the address pointer pointing at the first location
in memory on Page 1. See the section on the TSC2100 memory map for details of register locations
BIT 15
MSB
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LSB
R/W*
PG3
PG2
PG1
PG0
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
0
Figure 34. TSC2100 Command Word
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