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參數資料
| 型號： | TSC2100IRHBR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC32 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件頁數： | 18/77頁 |
| 文件大小： | 1079K |
| 代理商： | TSC2100IRHBR |
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TSC2100
SLAS378 NOVEMBER 2003
www.ti.com
25
D ADC/DAC SAMPLING RATE
The Audio Control 1 register (Register 00H, Page2) determines the sampling rates of the audio DAC and ADC, which
are scaled down from a reference rate (Fsref). The ADC and DAC can operate with either a common LRCK (equal
sampling rates) or separate ADWS and LRCK (unequal sampling rates). When the audio codec is powered up, it is by
default configured as an I2S slave with both the DAC and ADC operating at Fsref.
D WORD SELECT SIGNALS
The word select signal (LRCK, ADWS) indicates the channel being transmitted:
LRCK/ADWS = 0: left channel for I2S mode
LRCK/ADWS = 1: right channel for I2S mode
For other modes see the timing diagrams below.
Bitclock (BCLK) Signal
In addition to flexibility as master or slave mode, the BCLK can also be configured in two transfer modes—256S and
Continuous Transfer Modes, which are described below. These modes are set using BITD12/REG06h/Page2.
D 256S TRANSFER MODE
In the 256S mode, the BCLK rate always equals 256 times the maximum of the LRCK and ADWS frequencies. In the
256S mode, the combination of 48 ksps sampling rate (as selected by BITD13/REG06h/Page2) and leftjustified
mode is not supported.
D CONTINUOUS TRANSFER MODE
In the continuous transfer mode, the BCLK rate always equals two times the word length of the maximum of the LRCK
and ADWS frequencies.
D RIGHT-JUSTIFIED MODE
In right-justified mode, the LSB of the left channel is valid on the rising edge of the BCLK preceding the falling edge of
ADWS or LRCK. Similarly the LSB of the right channel is valid on the rising edge of the BCLK preceding the rising edge
of ADWS or LRCK.
BCLK
ADWS/
LRCK
DIN/
DOUT
n
n1
1
0
n
n1
1
0
LSB
MSB
n22
2
n2
1/fs
Left Channel
Right Channel
Figure 23. Timing Diagram for Right-Justified Mode
D LEFT-JUSTIFIED MODE
In leftjustified mode, the MSB of the right channel is valid on the rising edge of the BCLK, following the falling edge of
ADWS or LRCK. Similarly the MSB of the left channel is valid on the rising edge of the BCLK following the rising edge of
ADWS or LRCK.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TSC2100IRHBRG4 | 功能描述:觸摸屏轉換器和控制器 Prog 4-Wire w/Ster Codec & Hdph/Spk Amp RoHS:否 制造商:Microchip Technology 類型:Resistive Touch Controllers 輸入類型:3 Key 數據速率:140 SPS 分辨率:10 bit 接口類型:4-Wire, 5-Wire, 8-Wire, I2C, SPI 電源電壓:2.5 V to 5.25 V 電源電流:17 mA 工作溫度:- 40 C to + 85 C 封裝 / 箱體:SSOP-20 |
| TSC2100IRHBRMULT1 | 制造商:Texas Instruments 功能描述: |
| TSC2101 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:AUDIO CODEC WITH INTERATED HEADPHONE SPEAKER AMPLIFIER AND TOUCH SCREEN CONTROLLER |
| TSC2101_07 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:AUDIO CODEC WITH INTEGRATED HEADPHONE, SPEAKER AMPLIFIER AND TOUCH SCREEN CONTROLLER |
| TSC2101_08 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:AUDIO CODEC WITH INTEGRATED HEADPHONE, SPEAKER AMPLIFIER AND TOUCH SCREEN CONTROLLER |
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