
TSC2111
SLAS495A JUNE 2006 REVISED OCTOBER 2007
www.ti.com
24
Table 2. Fsref = 48 kHz
MCLK (MHz)
P
J
D
ACHIEVED FSREF
% ERROR
2.048
1
48
0
48000.00
0.0000
3.072
1
32
0
48000.00
0.0000
4.096
1
24
0
48000.00
0.0000
6.144
1
16
0
48000.00
0.0000
8.192
1
12
0
48000.00
0.0000
12.0
1
8
1920
48000.00
0.0000
13.0
1
7
5618
47999.71
0.0006
16.0
1
6
1440
48000.00
0.0000
19.2
1
5
1200
48000.00
0.0000
19.68
1
4
9951
47999.79
0.0004
48.0
4
8
1920
48000.00
0.0000
To externally observe the PLL function, the GPIO2 pin can be set up as the clock monitor (set D2 = 1, register
22h, page 2). Note that besides setting up the PLL and GPIO2, the audio ADC or DAC must be enabled for
the PLL output to appear at the GPIO2.
Example 1:
D Start from power up (with the proper sequence)
D Make sure MCLK is provided and /PWR_DWN and /RESET are both high
D Set and enable PLL
D Connect and power up (do not unmute anything) ADC or DAC or both, for instance:
Page2/Reg03h to C530h or C510h (default is C500h) to connect MICSEL to ADC
Page2/Reg05h to FDFCh (default is FFFCh) to power up ADC.
D Set Page2/Reg22h to 0004h to output PLL to GPIO2 pin.
MONO AUDIO ADC
Analog Front End
The analog front end of the audio ADC consists of an analog MUX and a programmable gain amplifier (PGA).
The MUX can connect either of the Headset Input (MICIN_HED), Handset Input (MICIN_HND), AUX1 and
AUX2 signal through the PGA to the ADC for audio recording. The Cell-phone Input (CP_IN) can also be
connected to ADC through a PGA at the same time. This enables recording of conversation during a cell-phone
call. The TSC2111 also has an option of choosing MICIN_HED/MICIN_HND and AUX1/AUX2 as differential
input pair. The TSC2111 also includes two microphone bias circuits which can source up to 5 mA of current,
and are programmable to a 2 V, 2.5 V or 3.3 V level for Headset and 2 V or 3.3 V level for handset.
Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering,
requirements for analog anti-aliasing filtering are very relaxed. The TSC2111 integrates a second order analog
anti-aliasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital decimal filter, provides
sufficient anti-aliasing filtering without requiring any external components.
The PGA, for microphone and AUX Inputs, allows analog gain control from 0 dB to 59.5 dB in steps of 0.5 dB.
The PGA gain changes are implemented with an internal soft-stepping. This soft-stepping ensures that volume
control changes occur smoothly with no audible artifacts. Upon reset, the PGA gain defaults to a mute condition,
and upon power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag (D0
control register 04H/Page 2) is set whenever the gain applied by PGA equals the desired value set by the
register. The soft-stepping control can be disabled by programming D15=1 in register 1DH of Page 2. When
soft stepping is enabled and ADC power down register is written, MCLK should be running to ensure that
soft-stepping to mute has completed. MCLK can be shut down once Mic PGA power down flag is set.
The PGA, for Cell phone Input (CP_IN) allows gain control from –34.5 dB to 12 dB in steps of 0.5 dB. The PGA
gain changes are implemented with an internal softstepping. This soft-stepping ensures that volume control
changes occur smoothly with no audible artifacts. Upon reset, the PGA gain defaults to a mute condition, and