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參數(shù)資料
| 型號： | TSC87C52-16IJD |
| 英文描述： | CMOS 0 to 33 MHz Programmable 8朾it Microcontroller |
| 中文描述： | 的CMOS 0至33 MHz的可編程微控制器8朾它 |
| 文件頁數(shù)： | 23/24頁 |
| 文件大小： | 273K |
| 代理商： | TSC87C52-16IJD |
TSC87C52
23
MATRA MHS
Rev. C – 10 Sept 1997
Preliminary
Clock Waveforms
DATA
PCL OUT
DATA
PCL OUT
DATA
PCL OUT
SAMPLED
SAMPLED
SAMPLED
STATE4
STATE5
STATE6
STATE1
STATE2
STATE3
STATE4
STATE5
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
FLOAT
FLOAT
FLOAT
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
INDICATES ADDRESS TRANSITIONS
EXTERNAL PROGRAM MEMORY FETCH
FLOAT
DATA
SAMPLED
DPL OR Rt OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
PCL OUT (EVEN IF PROGRAM
MEMORY IS INTERNAL)
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
OLD DATA
NEW DATA
P0 PINS SAMPLED
P1, P2, P3 PINS SAMPLED
P1, P2, P3 PINS SAMPLED
P0 PINS SAMPLED
RXD SAMPLED
INTERNAL
CLOCK
XTAL2
ALE
PSEN
P0
P2 (EXT)
READ CYCLE
WRITE CYCLE
RD
P0
P2
WR
PORT OPERATION
MOV PORT SRC
MOV DEST P0
MOV DEST PORT (P1. P2. P3)
(INCLUDES INTO. INT1. TO T1)
SERIAL PORT SHIFT CLOCK
TXD (MODE 0)
DATA OUT
DPL OR Rt OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
P0
P2
RXD SAMPLED
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins,
however, ranges from 25 to 125ns. This propagation delay is dependent on variables such as temperature and pin
loading. Propagation also varies from output to output and component. Typically though (T
A
=25 C fully loaded) RD
and WR propagation delays are approximately 50ns. The other signals are typically 85ns. Propagation delays are
incorporated in the AC specifications.
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| TSC87C52-16IJR | CMOS 0 to 33 MHz Programmable 8朾it Microcontroller |
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| TSC87C52-16IKD | CMOS 0 to 33 MHz Programmable 8朾it Microcontroller |
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