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參數資料
| 型號： | TSL238T |
| 廠商： | AMS-TAOS USA Inc |
| 文件頁數： | 8/13頁 |
| 文件大小： | 624K |
| 描述： | IC LIGHT TO FREQUENCY CONV 4-TMB |
| 標準包裝： | 1 |
| 系列： | * |
| 其它名稱： | TSL238-TDKR |
TSL238T
HIGH-SENSITIVITY
LIGHT-TO-FREQUENCY CONVERTER
TAOS080G DECEMBER 2007
7
The LUMENOLOGY r Company
r
r
Copyright E 2007, TAOS Inc.
www.taosinc.com
APPLICATION INFORMATION
Measuring the Frequency
The choice of interface and measurement technique depends on the desired resolution and data-acquisition
rate. For maximum data-acquisition rate, period-measurement techniques are used.
Period measurement requires the use of a fast reference clock with available resolution directly related to the
reference-clock rate. The technique is employed to measure rapidly varying light levels or to make a fast
measurement of a constant light source.
Maximum resolution and accuracy may be obtained using frequency-measurement, pulse-accumulation,
or integration techniques. Frequency measurements provide the added benefit of averaging out random- or
high-frequency variations (jitter) resulting from noise in the light signal. Resolution is limited mainly by available
counter registers and allowable measurement time. Frequency measurement is well suited for slowly varying
or constant light levels and for reading average light levels over short periods of time. Integration, the
accumulation of pulses over a very long period of time, can be used to measure exposure the amount of light
present in an area over a given time period.
Output enable (OE
) places the output in a high-impedance state for multiple-unit sharing of a microcontroller
input line. When the OE
line goes low, the device resynchronizes the output to an integration cycle. The rising
edge of the output signal (OUT) will occur exactly one period of the output frequency after OE
goes low.
PCB Pad Layout
Suggested PCB pad layout guidelines for the T package are shown in Figure 10.
1.50
2.90
0.90
1.00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
Figure 10. Suggested T Package PCB Layout
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