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參數資料
| 型號： | TSRD1003G |
| 元件分類： | 通信、網絡模塊及開發工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數據通信 |
| 文件頁數： | 1/4頁 |
| 文件大小： | 59K |
| 代理商： | TSRD1003G |
Product Brief
February 2002
TSRD1003G
~1.06—3.2 Gbits/s Serializer and Deserializer (Macro)
Features
I
Designed to operate in Ethernet, fibre channel,
InfiniBand
, and SONET/SDH (synchronous digi-
tal hierarchy) applications.
I
Selectable data rate (1.06 Gbits/s—3.2 Gbits/s).
I
100 MHz—168 MHz reference clock frequency
range.
I
16-bit or 20-bit parallel I/O interface in full-rate
mode.
I
Programmable control and configuration interface
to define the various device configurations.
I
Analog modularity and digital library interface for
design flexibility.
I
Automatic lock-to-reference in absence of receive
data.
I
CML high-speed interface I/O for use with back-
plane or cable media.
I
Programmable transmit pre-emphasis optimized
for backplane applications.
I
Requires one external resistor for bias current gen-
eration.
I
Requires no external components for clock recov-
ery and frequency synthesis.
I
105 mW per transceiver (typical).
I
Low powerdown dissipation.
I
Half amplitude mode for reduced power consump-
tion in chip-to-chip applications.
I
1.5 V ± 5% power supply.
I
1.8 V ± 5% power supply option for differential
high-speed I/O circuits.
I
0 °C—125 °C junction temperature.
Potential Applications
Drives chip-to-chip and across backplanes.
I
SONET
I
Fibre Channel
I
InifiniBand
I
10 Gbit Ethernet (XAUI)
Description
The TSRD1003G is a high-speed serializer/deserial-
izer (SERDES) macrocell. This macro cell includes a
current mode logic (CML) high-speed serial interface
and makes use of a proprietary CDR architecture
along with the sharing of a PLL across multiple RX
and TX channels to reduce area and power con-
sumption. These characteristics make it suitable for
applications that require high channel counts.
Figure 1. TSRD1003G for COM2/2H
D
PLL
S
D19
C
D0
P
L
M
CKOUT
DIN
R
X
REFCLK
DOUT
L
D19
DO
DIV
T
X
DIGITAL
LIBRARY
INTERFACE
SERIAL
INTERFACE
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