
Functional Description
3 - 22
TUA6030, TUA6032
Wireless Components
Specification, January 2002
SCL remains high. All further information transfer takes place during SCL = low,
and the data is forwarded to the control logic on the positive clock edge.
should be referred to for the following description. All telegrams are transmitted
byte-by-byte, followed by a ninth clock pulse, during which the control logic
returns the SDA line to low (acknowledge condition). The first byte is comprised
of seven address bits. These are used by the processor to select the PLL from
several peripheral components (address select). The LSB bit (R/W) determines
whether data are written into (R/W = 0) or read from (R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the MSB bit of the
first or third data byte determines whether a divider ratio or control information
is to follow. In each case the second byte of the same data type has to follow
the first byte. Appropriate setting of the test bits will decide whether the band-
).
If the address byte indicates a READ operation, the PLL generates an acknowl-
edge and then shifts out the status byte onto the SDA line. If the processor gen-
erates an acknowledge, a further status byte is output; otherwise the data line
is released to allow the processor to generate a stop condition. The status word
consists of three bits from the A/D converter, the lock flag and the power-on flag.
Four different chip addresses can be set by an appropriate DC level at pin AS
While the supply voltage is applied, a power-on reset circuit prevents the PLL
from setting the SDA line to low, which would block the bus. The power-on reset
flag POR is set at power-on and if VCC falls below 3.2 V. It will be reset at the
end of a READ operation.