- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98305 > TVP5040CPFP (TEXAS INSTRUMENTS INC) COLOR SIGNAL DECODER, PQFP80 PDF資料下載
參數(shù)資料
| 型號： | TVP5040CPFP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 59/109頁 |
| 文件大小： | 568K |
| 代理商： | TVP5040CPFP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁當前第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁
2–37
2.8.10 Parallel Host Interface Register Map
The parallel host interface (PHI) module contains only four registers that are directly accessible to the host (see
Figure 2–36). The address register holds an indirect address for internal register access. When the host accesses
the data register the PHI module reads or writes the internal register selected by the indirect address register. Two
other registers are provided for direct access. The FIFO register provides direct access to the VBI FIFO. The other
direct access register is the status/interrupt register. This register contains the state of the interrupt sources.
00
Address Register
A[1:0]
01
Data Register
10
FIFO
11
Status Register
Figure 2–36. PHI Address Register Map
Normally, read or write operations require two accesses. To read the FIFO register, set A[1:0] to 2’b10, and perform
a read cycle. The FIFO read data is placed on the D[7:0] bus. To read/write the status/interrupt register, set A[1:0]
to 2’b11 and perform the read/write cycle. The read/write data is appropriately muxed to/from the external data bus.
Indirect register read/write
All PHI accesses except for the VBI FIFO and the status/interrupt register require a two-step operation. To access
an indirect register, the desired internal address must first be written to the address register of the PHI. This is done
by setting A[1:0] to 00 and performing a write cycle with D[7:0] = indirect register address. To write to an indirect
register, the second step consists of writing the desired data to PHI address 01. To read an indirect register, the second
step consists of reading the requested data from address 01.
Read Indirect Register
Step 1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write register address
0
Register address
Step 2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Read register data
0
1
Data from register
Write Indirect Register
Step 1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write register address
0
Register address
Step 2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Write register data
0
1
Data to register
Latency
PHI accesses to indirect addresses 00-8F require special consideration due to response latencies of up to 64
s for
these addresses. Latency occurs between steps 1 and 2 for a read operation, and following step 2 for a write
operation. To avoid violating PHI cycle time requirements the host can poll the cycle complete bit in the PHI status
register following step 1 for a read or step 2 for a write. Alternatively, the cycle complete enable bit in the interrupt
enable register (indirect address C1) can be set to generate an interrupt for the host when an access has been
completed.
PHI accesses to indirect addresses 90-CF occur with minimal latency and interrupts are not generated for the
completion of access cycles to these addresses.
相關PDF資料 |
PDF描述 |
|---|---|
| TVP5040PFP | COLOR SIGNAL DECODER, PQFP80 |
| TVP5041PFP | COLOR SIGNAL DECODER, PQFP80 |
| TVP5146M1PFP | COLOR SIGNAL DECODER, PQFP80 |
| TVP5146M2IPFPR | COLOR SIGNAL DECODER, PQFP80 |
| TVP5146M2IPFP | COLOR SIGNAL DECODER, PQFP80 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TVP5040CPFPG4 | 功能描述:IC NTSC/PAL VIDEO DECODER 80TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| TVP5040EVM | 制造商:Texas Instruments 功能描述:EVAL BD TVP5040EVM USER S GUIDE - Bulk |
| TVP5145 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NTSC/PAL/SECAM/Component Digital Video Decoder With Macrovision(TM) Detection |
| TVP5145EVM | 制造商:Texas Instruments 功能描述:TVP5145EVM - Bulk |
| TVP5145PFP | 功能描述:視頻 IC NTSC/PAL/SECAM/ Comp Dig Vid Dec RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。