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| 型號： | TVP7001PZPRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 8/35頁 |
| 文件大小： | 504K |
| 代理商： | TVP7001PZPRG4 |
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Power
Reset
I2C
5 ms
1
s
1
s
Control Registers
SLES164 – FEBBRUARY 2006
Table 4. Reset Sequence
SIGNAL NAME
DURING RESET
RESET COMPLETED
ROUT[9:0], BOUT[9:0], BOUT[9:0]
High impedance
Output
HSOUT, VSOUT, SOGOUT
High impedance
Output
DATACLK
High impedance
Output
Figure 7. Reset Timing
The TVP7001 is initialized and controlled by a set of internal registers that define the operating parameters of the
entire device. Communication between the external controller and the TVP7001 is through a standard I2C host
port interface, as described earlier.
Table 5 shows the summary of these registers. Detailed programming information for each register is described
in the following sections.
Table 5. Control Registers Summary(1)(2)
Register Name
I2C Subaddress
Default
R/W
Chip Revision
00h
R
PLL Divide MSB
01h
69h
R/W
PLL Divide LSB
02h
D0h
R/W
PLL Control
03h
48h
R/W
Phase Select
04h
80h
R/W
Clamp Start
05h
80h
R/W
Clamp Width
06h
80h
R/W
HSYNC Output Width
07h
20h
R/W
Blue Fine Gain
08h
80h
R/W
Green Fine Gain
09h
80h
R/W
Red Fine Gain
0Ah
80h
R/W
Blue Fine Offset
0Bh
80h
R/W
Green Fine Offset
0Ch
80h
R/W
Red Fine Offset
0Dh
80h
R/W
Sync Control 1
0Eh
40h
R/W
PLL and Clamp Control
0Fh
4Eh
R/W
(1)
Register addresses not shown in the register map summary are reserved and must not be written to.
(2)
Writing to or reading from any value labeled “Reserved” register may cause erroneous operation of the TVP7001. For registers with
reserved bits, a 0b must be written to reserved bit locations unless otherwise stated.
16
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