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參數資料
| 型號： | TZA1047HL/M1B |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.4 MM HEIGHT, PLASTIC, MS-026, SOT314-2, LQFP-64 |
| 文件頁數： | 2/69頁 |
| 文件大小： | 324K |
| 代理商： | TZA1047HL/M1B |
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9397 750 14664
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 1 June 2005
10 of 69
Philips Semiconductors
TZA1047
Preprocessor IC for CD and DVD rewritable
7.4 Input circuit
Refer to Figure 4.
The Input circuit comprises a voltage reference circuit, sample-and-hold circuit, and a
programmable gain amplier. The input signals to the Input circuit are VIA to VIH, and can
be either currents or voltages. The signal names correspond to the PDIC segments shown
termination resistor that is selectable by the control word LDSEG[1:0]. The currents of
input signals, for example from the TZA1045, are converted to voltages across the input
termination resistors.
The voltage reference circuit is a DAC which is programmable by control word VSEG[3:0]
to allow different PDICs to be supported. The voltage reference circuit has a sufciently
large sink capability for the 150
termination resistors, allowing the TZA1047 to work
with a characteristically terminated ex connection to the OPU.
Note that when the TZA1047 is in Standby mode (STBY = 1), VREF and the input resistors
remain active to allow the TZA1045 to deliver current to the TZA1047 without the risk of
‘latch-up’.
The reference voltage is subtracted from the input signals and the resulting signals VRA
to VRH are optionally sampled by a sample-and-hold circuit. The sampling signals TH1
and TH2 originate either directly from the codec IC or from the EFMTIM circuit. The
resultant signals VSA to VSH are sent to the Distributor for further processing. If sampling
is disabled (bit SMPLON = 0), both switches remain closed and the sample-and-hold
circuit is transparent.
The central signals VRA to VRD are amplied for DPD use at a gain programmable by
control word GSEG[1:0]. The resultant four signals VUA to VUD go to the DPD circuit. The
GSEG gain is enabled when bit DPD = 1 and is disabled, to save power, when bit
DPD=0.
The input signal range for VIA to VIH
V
ref is 1 V maximum.
Fig 4.
Input circuit.
001aab193
REFERENCE
CIRCUIT
TH1
DPD
GSEG
VSEG
TH2
SAMPLE-AND-HOLD (8
×)
+
VREF
VRA to VRH
VRA to VRD
VSA to VSH
VUA to VUD
LDSEG
VREF
VIA to VIH
R0
(8
×)
R1
(8
×)
R2
(8
×)
R3
(8
×)
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