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參數(shù)資料
| 型號： | TZA1049TH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 封裝： | PLASTIC, HEAT SINK, SOP-28 |
| 文件頁數(shù)： | 14/17頁 |
| 文件大小： | 104K |
| 代理商： | TZA1049TH |
2004 Mar 09
6
Philips Semiconductors
Product specication
4-channel BTL driver for CD/DVD drives
TZA1049
7
FUNCTIONAL DESCRIPTION
7.1
General notes
1. The integral thermal shut-down circuit mutes the
output current when the chip temperature reaches
175
°C (typical). The hysteresis is set to 25 °C
(typical), so the circuit will restart when the chip
temperature falls to 150
°C (typical).
2. Mute mode is activated when the voltage at pin MUTE
is below 0.5 V, and deactivated when the voltage at
pin MUTE is above 1.2 V. In mute mode, both positive
and negative output terminals will be at
high-impedance state. However, the 3.3 V and 1.8 V
outputs are not affected.
3. It is recommended that a 220
F decoupling capacitor
is connected between pins VCC and pin GND and
physically located as close as possible to these supply
pins.
4. The positive outputs of the focus, radial and sled driver
channels are in phase with their respective input
signals. The positive output of the spindle driver
channel is in phase with the input signal on
pin MOTIN1.
5. The values of the resistors connected to each input
channel must be equal to, or larger than, 4.7 k
to
ensure that the gain of each input stage is less than, or
equal to 1.
6. The GND pins are internally connected to heat
dissipation fins within the package. You must ensure
that these pins are connected to an external ground.
7. The 1.65 V bias voltage output from pin VBIASOUT is
derived from the internal 3.3 V generator/regulator,
and will be affected by any variation in the 3.3 V
generator/regulator voltage.
TZA1049TH
VCC
VOUT3.3
RADOUTN
VFBIN3.3
FOCOUTP
VOUT1.8
GND
VFBIN1.8
FOCOUTN
MUTE
RADOUTP
RADIN
VCC
FOCIN
VCC
SLIN
SLOUTP
VBIASIN
SLOUTN
GND
VBIASOUT
MOTOUTP
MOTBIAS
MOTOUTN
MOTIN1
VCC
MOTIN2
mce479
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
18
17
20
19
22
21
24
23
26
25
28
27
Fig.2 Pin configuration.
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