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| 型號(hào)： | U2893B |
| 英文描述： | Modulation PLL for GSM, DCS and PCS Systems |
| 中文描述： | 調(diào)制鎖相環(huán)用于GSM，DCS和PCS系統(tǒng) |
| 文件頁(yè)數(shù)： | 12/14頁(yè) |
| 文件大小： | 294K |
| 代理商： | U2893B |
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U2893B
TELEFUNKEN Semiconductors
Rev. A1, 29-Jan-76
Preliminary Information
12 (14)
Measurements
Modulation-Loop Settling Time
As valid for all PLL loops the settling time depends on
several factors. The following figure is an extraction from
measurements performed in an arrangement like the ap-
plication circuit. It shows that a loop settling time of a few
s can be achieved.
CPC: 1 k
to GND
CPC ‘open’
Vertical: VCO tuning voltage 1 V/Div
Horizontal: Time 1 s/Div
Figure 17.
Modulation Spectrum & Phase Error
The figure of the TX spectrum and the phase error dis-
tribution, respectively, shows the suitability of the
modulation-loop concept for GSM.
Vertical: VRef. level = 28.6 dBm, 10 dBm/Div
Horizontal: Center = 900 MHz, VBW, RBW = 30 kHz,
400 kHz/Div
Figure 18.
Figure 19.
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