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參數資料
| 型號： | U4240B |
| 英文描述： | AM - RECEIVER |
| 中文描述： | 上午-接收機 |
| 文件頁數： | 2/8頁 |
| 文件大?。?/td> | 112K |
| 代理商： | U4240B |
TELEFUNKEN Semiconductors
U4240B
Rev. A1: 12.07.1995
2 (8)
Pin Description
18
10
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
U4240B
93 7721 e
DIP 18
1
2
3
4
5
6
7, 8
9
10
11
12
13
14
15
16, 17
18
DIP 20
1
2
4
5
6
7
8, 9
10
11
12
13
14
15
16
17, 19
20
3, 18
Function
Mixer output
Standby switch
IF amplifier input
V
REF
Low pass filtering
AF output
AGC time constant
Low pass filtered AF output
IF output
Field strength indicator
Oscillator output
Oscillator tank reference output
Oscillator tank input
V
S
RF input
GND
Not connected
Controlled RF Preamplifier, Pin 7
The RF preamplifier is built up differentially in order to
achieve the best possible large signal handling capability.
Special care was taken to reduce the input stage noise.
Balanced Mixer, Pin 1
The mixer is a double balanced type with a single ended
output.
Controlled Oscillator, Pins 13 and 14
The oscillator employs temperature compensation,
simple varicap and coil connection. The amplitude of the
oscillator is controlled to low values, in order to support
AM varactor diodes. The LO-buffer supports the
U428xBM PLL-family.
Controlled IF Amplifier, Pin 3
The IF amplifier consists of two controlled gain cells
coupled by capacitive means. Internal band pass filtering
reduces higher order products and THD.
AM-IF Output, Pin 10
For AM stereo application and for stop signal generation
by IF counting Pin 10 provides a non limited but ampli-
tude controlled IF signal of about 280 mV.
Balanced Full-Wave Detector, Pin 5
The detector consists of a Gilbert cell that multiplies the
limited carrier signal with the IF output signal and there-
fore employs a full wave rectification. Second or higher
order products at the output are internally low pass
filtered.
AF Amplifier, Pin 6
The AF amplifier has two different outputs. They provide
different output resistances for simplifying applications.
For a high end application Pin 6 provides a 3.5 k output
resistor to support a second order low pass filter. Pin 9
provides additional 12 k for a simple first order low pass
filter.
AGC, Pin 8
The AGC block generates the AGC voltage that is to be
smoothed at Pin 8. The capacitor at Pin 8 defines the time
constant. The voltage at Pin 8 is buffered to control the
internal gain stages with different delay. The control volt-
age is available at Pin 11 (field strength indication).
Standby Switch, Pin 2
The whole circuit can be powered down by the standby
switch. This mode can be achieved by a dc voltage higher
than 3.5 V at Pin 2.
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