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參數(shù)資料
| 型號： | U4280 |
| 英文描述： | 2-WIRE FACTORY PROGRAMMED W/TIN PLATING |
| 中文描述： | 調幅/調頻-鎖相環(huán) |
| 文件頁數(shù)： | 5/9頁 |
| 文件大小： | 172K |
| 代理商： | U4280 |
U4280BM
Preliminary Information
TELEFUNKEN Semiconductors
Rev. A1, 10-Apr-97
5 (9)
Electrical Characteristics
V
DD
= 5 V, T
amb
= 25
°
C, otherwise specified
Parameters
Supply voltage range
Quiescent supply voltage
FM input sensitivity
Test Conditions / Pins
Symbol
V
DD
I
DD
Min.
4.5
Typ.
5.0
6.0
Max.
5.5
11.6
Unit
V
mA
Pin 1
Pin 1
Pin 10
R
G
= 50
f
i
= 30 to 60 MHz
f
i
= 70 to 120 MHz
f
i
= 120 to 130 MHz
R
G
= 50
f
i
= 0.4 to 35 MHz
R
G
= 50
f
i
= 0.1 to 15 MHz
V
I
V
i
V
i
50
25
50
mV
mV
mV
AM input sensitivity
Pin 12
V
i
25
mV
Oscillator input sensitivity
Pin 18
V
i
100
2
mV
Adjustable divider
1)
Switching output, PRT
65535
Pin 5
I
H
= 1 mA
I
L
= 1 mA
I
L
= 0.1 mA
V
OH
V
OL
V
OL
V
DD
– 0.4
0.4
0.1
V
V
V
SWO1 to SWO3, AM/FM
(open drain outputs)
Pins 6 to 9
I
L
= 1 mA
I
L
= 0.1 mA
V
OL
V
OL
0.4
0.1
V
V
LD (open drain)
Pin 17
I
L
= 1 mA
V
OL
0.4
V
Phase detector
PDFM
Pin 14
Output current 1
Output current 2
I
O1
I
O2
±
400
±
100
±
500
±
125
±
600
±
150
A
A
PDAM
Pin 15
Output current 1
Output current 2
Pins 14 and 15 to V
DD
Pins 14 and 15 to GND
H input voltage, Pins 2 and 3
L input voltage, Pins 2 and 3
I
SDAH
= 3 mA
I
O1
I
O2
I
13,16
I
13,16
V
IH
V
IL
V
O
f
SCL
±
75
±
20
±
100
±
25
–1
0.5
±
100
±
30
–2
A
A
Analog output
0.1
3
0
mA
mA
V
V
V
kHz
I
2
bus inputs SCL, SDA
V
DD
1.5
0.4
110
Output voltage
Clock frequency
Bus timing
Rise time SCL, SDA
Fall time SCL, SDA
“H” phase SCL
“L” phase SCL
Waiting time START
Set up time START
Set up time STOP
Set up time DATA
Hold time DATA
Pin 2
0
t
r
t
f
t
H
t
L
1
s
300
ns
4
s
s
s
s
s
4.7
4
4
4.7
250
0
t
wSTA
t
hSTA
t
sSTA
t
sDAT
t
hDAT
ns
s
1)
FM input frequency is additionally divided by two (Pin 10).
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