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參數資料
| 型號： | U6207B-FPG3 |
| 英文描述： | 1.3 GHz PLL with I2C Bus for TV Tuner |
| 中文描述： | 1.3千兆赫的電視調諧器鎖相環與I2C總線 |
| 文件頁數： | 3/8頁 |
| 文件大小： | 112K |
| 代理商： | U6207B-FPG3 |
U6207B
TELEFUNKEN Semiconductors
Rev. A1, 29-May-96
3 (8)
Electrical Characteristics
Test conditions (unless otherwise specified) V
S
= 5 V, T
amb
= 25
°
C
Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
Supply current
Pin 10
SW 1, 2, 7 = 0; PSC = 1
SW 1, 2, 7 = 0; PSC = 0
Is
Is
32
22
42
28
52
35
mA
mA
Input sensitivity
fi = 80 - 1000 MHz
fi = 1300 MHz
fi = 10 - 220 MHz
Maximum input signal
Open collector switching outputs
(SW 1,2,7) Pin 9,8,6
Reserve current
Saturation voltage
Phase detector output
Charge pump current “H”
Charge pump current “L”
Charge pump leakage
current
Bus inputs (
SDA,SCL)
Input voltage
PSC = 1
PSC = 1
PSC = 0
PSC = 0 / 1
Pin 11
Pin 11
Pin 11
Pin 11
Vi
1)
Vi
1)
Vi
1)
Vimax
1)
10
40
10
mV
mV
mV
mV
315
VH = 13.5 V
IL = 10 mA
IRH
VSL
2)
10
0.5
A
V
5I = 1, VPD = 2 V, Pin 1
5I = 0, VDP = 2 V, Pin 1
T0 = 0, VPD = 2 V, Pin 1
IPDH
IPDL
IPDTRI
±
180
±
50
±
5
A
A
nA
Pin 4, 5
Pin 4, 5
Vi “H”
Vi “L”
li “H”
li “L”
VSDA
“L”
3
5.5
1.5
10
V
V
A
A
V
Input current
VSCL “H” = Vs, Pin 4, 5
VSCL “L” = 0 V, Pin 4, 5
ISDA “L” = 2 mA , Pin 4
–20
Output voltage SDA
(open collector)
Address selection (
AS)
Input current
0.4
VAS “H” = Vs
VAS “L” = 0 V
Pin 7
Pin 7
liAS “H”
liAS “L”
–100
10
A
A
Bus timing
Rise time SDA, SCL
Fall time SDA, SCL
Clock frequency SCL
Clock “H” Pulse
Clock “L” Pulse
Hold time start
Set-up time stop
Set-up time data
Hold time data
tR
tF
15
15
100
s
s
fSCL
tHIGH
tLOW
tHSTA
tSSTO
tSDAT
tHDAT
0
4
4
4
4
kHz
s
s
s
s
s
s
0.3
0
1)
2)
RMS-voltage calculated from the measured available power on 50 .
Tested with one switch active.
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