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參數資料
| 型號： | U6209B-GFPG3 |
| 英文描述： | 1.3 GHz PLL for TV- and VCR- Tuner |
| 中文描述： | 1.3千兆赫PLL的電視和錄像機，調諧器 |
| 文件頁數： | 2/11頁 |
| 文件大?。?/td> | 155K |
| 代理商： | U6209B-GFPG3 |
U6209B
TELEFUNKEN Semiconductors
Rev. A2, 30-Aug-96
Preliminary Information
2 (11)
Pin Configuration
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PD
Q1
Q2
SDA
95 10758
SCL
P3
P2
P1
RFi
RFi
V
S
P4
AS
P0
GND
VD
Figure 2.
5
6
13
14
SCL
P3
RFi
RFi
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Port output (open collector)
RF input
RF input
Clock
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Circuit Description
The U6209B is a single-chip PLL designed for TV and
VCR receiver systems. It consists of a bridgeable
divide-by-8 prescaler with an integrated preamplifier, a
15-bit programmable divider, a crystal oscillator and a
reference divider with two selectable divider ratios
(512 / 1024), and a phase/frequency detector together
with a charge pump which drives the tuning amplifier.
Only one external transistor is required for varactor-line
driving. The device can be controlled via I
2
C bus format.
There are four programmable addresses selectable,
programmed by applying a specific input voltage to the
address-select input, enabling the use of up to four
synthesizers in a system. Five open collector output port
functions are included which are capable of sinking at
least 10 mA.
Oscillator frequency calculation:
fvco = PSF x SF x frefosc / 1024
fvco: Locked frequency of voltage controlled oscillator
PSF : Scaling factor of prescaler (1 or 8)
SF :
Scaling factor of programmable 15-bit divider
frefosc :Reference oscillator frequency:
3.2/4 MHz crystal or external reference frequency
In addition, there are port outputs available for band-
switching and other purposes.
Application
A typical application is shown on page 10. All input /
output interface circuits are shown on page 9.
Some special features which are related to test- and
alignment procedures for tuner production are explained
together within the following I
2
C bus mode description.
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相關代理商/技術參數 |
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| U6220B | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:1.3 GHz PLL for TV- and VCR- Tuner |
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