- 您現在的位置：買賣IC網 > PDF目錄382706 > U6209B 1.3 GHz PLL for TV- and VCR- Tuner PDF資料下載
參數資料
| 型號： | U6209B |
| 英文描述： | 1.3 GHz PLL for TV- and VCR- Tuner |
| 中文描述： | 1.3千兆赫PLL的電視和錄像機，調諧器 |
| 文件頁數： | 5/11頁 |
| 文件大小： | 155K |
| 代理商： | U6209B |
U6209B
Preliminary Information
TELEFUNKEN Semiconductors
Rev. A2, 30-Aug-96
5 (11)
Functional Description
The U6209B is programmed via a 2–wire I
2
C bus data
format. The three bus input Pins 4, 5, 10 are used as SDA,
SCL and address select inputs. The data includes the
scaling factor SF (15 bit) and port output information.
There are some additional functions included for testing
of the device.
I
2
C - Bus Description
The U6209B is controlled via a 2-wire I
2
C bus format by
feeding data and clock signals into the SDA and SCL lines
respectively. The table ‘I
2
C–BUS DATA FORMAT’
describes the format of the data and shows how to select
the device address by applying a voltage at pin 10. When
the correct address byte has been received, the SDA line
is pulled low by the device during the acknowledge
period, and then also during the acknowledge periods,
when additional data bytes are programmed. After the
address transmission (first byte), data bytes can be sent to
the device. There are four data bytes requested to fully
program the device. The programmable divider latch is
loaded after the 8th clock pulse of the second divider byte
PDB2, the control and the port register latches are loaded
after the 8th clock pulse of the control byte CB1 respec-
tively post byte CB2. The table ‘I
2
C-BUS PULSE
DIAGRAM’ shows some possible data transfer exam-
ples.
The programmable divider bytes PDB1 and PDB2 are
stored in a 15-bit latch and control the division ratio of the
15-bit programmable divider. The control Byte CB1
enables the control of the the following special functions:
5I-bit switches between low and high charge pump
current
T1-bit enables divider test mode when it is set to
logic 1
T0-bit enables the charge pump to be disabled when
it is set to logic 1
RD1 and RD2-bit allow selection of the reference
divider ratio
PSC–bit switches prescaler off when it is set to
logic 0
OS-bit disables the charge pump drive amplifier out-
put when it is set to logic 1.
When T1 is set to logic 1, the programmable divider out-
put signal is switched to pin 7 and the reference divider
output signal is switched to pin 6. The OS-bit function
disables the complete PLL function. This enables tuner
alignment by supplying the tuning voltage directly via the
30-V supply voltage of the tuner. The control byte CB2
programs the port outputs P0-4; a logic 0 for high
impedance output (off) and a logic 1 for low impedance
output (on).
相關PDF資料 |
PDF描述 |
|---|---|
| U6209B-GFPG3 | 1.3 GHz PLL for TV- and VCR- Tuner |
| U6214B-AFP | Low power quad operational amplifier |
| U6215B-AFP | Analog IC |
| U6216B-FPG3 | Low power quad operational amplifier |
| U6218B-AFP | Low power quad operational amplifier |
相關代理商/技術參數 |
參數描述 |
|---|---|
| U6209B-FFP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| U6209B-GFPG3 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:1.3 GHz PLL for TV- and VCR- Tuner |
| U6220B | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:1.3 GHz PLL for TV- and VCR- Tuner |
| U6220B-APG3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| U6223B-AFP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
發布緊急采購，3分鐘左右您將得到回復。