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參數資料
| 型號： | U62H824PK35 |
| 英文描述： | x24 SRAM |
| 中文描述： | x24的SRAM |
| 文件頁數： | 1/10頁 |
| 文件大?。?/td> | 87K |
| 代理商： | U62H824PK35 |
U62H824
November 01, 2001
1
196 608 bit static CMOS RAM
35 ns Access Time
Fully static Read and Write
operations
Equal address and chip
enable access times
Single bit on-chip address
multiplexer
Active high and active low
chip enable inputs
Output enable controlled three-
state outputs
TTL/CMOS-compatible
Low power standby mode
Power supply voltage 5 V
Operating temperature range
0
°
C to 70
°
C
-40
°
C to 85
°
C
CECC 90000 Quality Standard
ESD protection > 2000 V
(MIL STD 883C M3015.7)
Latch-up immunity > 100 mA
Package: PLCC52
The U62H824 is a static RAM
manufactured using a CMOS pro-
cess technology. The device inte-
grates an 8K x 24 SRAM core with
multiple chip enable inputs, output
enable, and an externally control-
led single address pin multiplexer.
These functions allow for direct
connection
to
DSP56k Digital Signal Processor
Family and provide a very efficient
means for implementation of a
reduced parts count system requi-
ring no additional interface logic.
The avialability of multiple chip
enable (E1 and E2) and output
enable (G) inputs provides for
greater system flexibility when mul-
tiple devices are used. With either
chip enable unasserted, the device
will enter standby mode, useful in
low-power applications. A single
on-chip multiplexer selects A12 or
X/Y as the highest order address
input depending upon the state of
the V/S control input. This feature
the
Motorola
allows one physical static RAM
component to efficiently store pro-
gram and vector or scalar ope-
rands
by
dynamically
partitioning the RAM array.
Typical applications will logically
map vector operands into upper
memory with scalar operands
being stored in lower memory.
An application example is at the
end of this document for additional
information.
Multiple power and ground pins
have been utilized to minimize
effectes induced by output noice.
re-
Fast 8K x 24 SRAM
Pin Configuration
DQ23
DQ22
DQ21
VSS
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
VSS
DQ14
DQ13
Signal Name
Signal Description
A0 - A11
A12, X/Y
V/S
DQ0 - DQ23
E1, E2
G
W
VCC
VSS
NC
Address Inputs
Multiplexed Address
Address Multiplexer Control
Data Input / Output
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
Not Connected
Pin Description
For proper operation of the device, all V
SS
pins must be connected to ground.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
23 24 25 26 27 28 29 30 31 32 33
22
52 51 50 49 48 47
A
A
X
V
A
N
V
A
A
A
A
A
A
DQ0
DQ1
VSS
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ2
DQ9
DQ10
D
A
A
A
A
G
V
V
N
E
E
W
D
46
45
44
43
42
41
40
39
38
37
36
35
34
Features
Description
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