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參數資料
| 型號： | U630H64DK25 |
| 英文描述： | Low noise JFET dual operational amplifiers |
| 中文描述： | NVRAM中（EEPROM的基礎） |
| 文件頁數： | 1/14頁 |
| 文件大?。?/td> | 143K |
| 代理商： | U630H64DK25 |
1
November 01, 2001
U630H64
High-performance CMOS nonvola-
tile static RAM 8192 x 8 bits
25, 35 and 45 ns Access Times
12, 20 and 25 ns Output Enable
Access Times
Hardware STORE Initiation
(STORE Cycle Time < 10 ms)
Automatic STORE Timing
10
5
STORE cycles to EEPROM
10 years data retention in
EEPROM
Automatic RECALL on Power Up
Hardware RECALL Initiation
(RECALL Cycle Time < 20
μ
s)
Unlimited RECALL cycles from
EEPROM
Unlimited Read and Write to SRAM
Single 5 V
±
10 % Operation
Operating temperature ranges:
0 to 70 °C
-40 to 85
°
C
CECC 90000 Quality Standard
ESD characterization according
MIL STD 883C M3015.7-HBM
(classification see IC Code
Numbers)
Packages: PDIP28 (300 mil)
SOP28 (330 mil)
The U630H64 has two separate
modes of operation: SRAM mode
and nonvolatile mode, determined
by the state of the NE pin.
In SRAM mode, the memory ope-
rates as an ordinary static RAM. In
nonvolatile operation, data is
transferred in parallel from SRAM
to EEPROM or from EEPROM to
SRAM. In this mode SRAM
functions are disabled.
The U630H64 is a fast static RAM
(25, 35, 45 ns), with a nonvolatile
electrically
erasable
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation), or from
the
EEPROM to the SRAM (the
RECALL operation) are initiated
through the state of the NE pin.
The U630H64 combines the high
performance and ease of use of a
PROM
fast SRAM with nonvolatile data
integrity.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Pin Configuration
Pin Description
HardStore
8K x 8 nvSRAM
Top View
1
2
3
NE
A12
A7
VCC
W
n.c.
28
27
26
4
5
6
7
8
9
10
11
A6
A5
A4
A3
A2
A1
A0
A8
A9
A11
G
A10
E
DQ7
DQ6
25
24
23
22
21
20
19
18
12
13
14
DQ1
DQ2
VSS
DQ5
DQ4
DQ3
17
16
15
DQ0
PDIP
SOP
Signal Name
Signal Description
A0 - A12
DQ0 - DQ7
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Nonvolatile Enable
Power Supply Voltage
Ground
E
G
W
NE
VCC
VSS
Features
Description
相關PDF資料 |
PDF描述 |
|---|---|
| U630H64DK35 | Low noise JFET dual operational amplifiers |
| U630H64DK45 | NVRAM (EEPROM Based) |
| U630H64SC25 | Low noise JFET quad operational amplifier |
| U630H64SC35 | Low noise JFET quad operational amplifier |
| U630H64SC45 | NVRAM (EEPROM Based) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| U630H64DK35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
| U630H64DK45 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
| U630H64SC25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
| U630H64SC35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
| U630H64SC45 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
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