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參數資料
| 型號： | U631H64SK45 |
| 英文描述： | NVRAM (EEPROM Based) |
| 中文描述： | NVRAM中（EEPROM的基礎） |
| 文件頁數： | 1/12頁 |
| 文件大小： | 125K |
| 代理商： | U631H64SK45 |
1
November 01, 2001
U631H64
High-performance CMOS non-
volatile static RAM 8192 x 8 bits
25, 35 and 45 ns Access Times
12, 20 and 25 ns Output Enable
Access Times
Software STORE Initiation
(STORE Cycle Time < 10 ms)
Automatic STORE Timing
10
5
STORE cycles to EEPROM
10 years data retention in
EEPROM
Automatic RECALL on Power Up
Software RECALL Initiation
(RECALL Cycle Time < 20
μ
s)
Unlimited RECALL cycles from
EEPROM
Unlimited Read and Write to
SRAM
Single 5 V
±
10 % Operation
Operating temperature ranges:
0 to 70
°
C
-40 to 85
°
C
CECC 90000 Quality Standard
ESD characterization according
MIL STD 883C M3015.7-HBM
(classification see IC Code
Numbers)
Packages:PDIP28 (300 mil)
SOP28 (330 mil)
The U631H64 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The U631H64 is a fast static RAM
(25, 35, 45 ns), with a nonvolatile
electrically
erasable
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation), or from the
EEPROM to the SRAM (the
RECALL operation) are initiated
through software sequences.
The U631H64 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
PROM
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
SoftStore
8K x 8 nvSRAM
Pin Configuration
Pin Description
Top View
1
2
3
n.c.
A12
A7
VCC
W
n.c.
28
27
26
4
5
6
7
8
9
10
11
A6
A5
A4
A3
A2
A1
A0
A8
A9
A11
G
A10
E
DQ7
DQ6
25
24
23
22
21
20
19
18
12
13
14
DQ1
DQ2
VSS
DQ5
DQ4
DQ3
17
16
15
DQ0
PDIP
SOP
Signal Name
Signal Description
A0 - A12
DQ0 - DQ7
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
E
G
W
VCC
VSS
Features
Description
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