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參數資料
| 型號： | U632H64BS2K25G1 |
| 英文描述： | PowerStore 8K x 8 nvSRAM |
| 中文描述： | PowerStore 8K的× 8非易失 |
| 文件頁數： | 1/15頁 |
| 文件大小： | 225K |
| 代理商： | U632H64BS2K25G1 |
U632H64
1
August 15, 2006
STK Control #ML0047
Rev 1.1
PowerStore
8K x 8 nvSRAM
Pin Configuration
Pin Description
Top View
1
2
3
VCAP
A12
VCCX
W
HSB
28
27
26
4
5
6
7
8
9
10
11
A6
A5
A4
A3
A2
A1
A0
A8
A9
A11
G
A10
E
DQ7
DQ6
25
24
23
22
21
20
19
18
A7
12
13
14
DQ1
DQ2
VSS
DQ5
DQ4
DQ3
17
16
15
DQ0
SOP
Signal Name
Signal Description
A0 - A12
DQ0 - DQ7
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
Capacitor
Hardware Controlled Store/Busy
E
G
W
VCCX
VSS
VCAP
HSB
The U632H64 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The U632H64 is a fast static RAM
(25 ns), with a nonvolatile electri-
cally erasable PROM (EEPROM)
element incorporated in each static
memory cell. The SRAM can be
read and written an unlimited num-
ber of times, while independent
nonvolatile
data
EEPROM. Data transfers from the
SRAM to the EEPROM (the
STORE operation) take place auto-
matically upon power down using
charge stored in an external 100
μ
F capacitor. Transfers from the
EEPROM to the SRAM (the
RECALL operation) take place
automatically on power up. The
U632H64 combines the high per-
formance and ease of use of a fast
SRAM with nonvolatile data inte-
grity.
STORE cycles also may be initia-
ted under user control via a soft-
resides
in
ware sequence or via a single pin
(HSB).
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Features
Description
High-performance CMOS non-
volatile static RAM 8192 x 8 bits
25 ns Access Time
12 ns Output Enable Access
Time
I
CC
= 15 mA at 200 ns Cycle
Time
Automatic STORE to EEPROM
on Power Down using external
capacitor
Hardware or Software initiated
STORE
(STORE Cycle Time < 10 ms)
Automatic STORE Timing
10
5
STORE cycles to EEPROM
10 years data retention in
EEPROM
Automatic RECALL on Power Up
Software RECALL Initiation
(RECALL Cycle Time < 20
μ
s)
Unlimited RECALL cycles from
EEPROM
Single 5 V
±
10 % Operation
Operating temperature ranges:
0 to 70
-40 to 85
°
C
QS 9000 Quality Standard
ESD characterization according
MIL STD 883C M3015.7-HB
(classification see IC Code
Numbers)
RoHS compliance and Pb- free
Package: SOP28 (330 mil)
°
C
Not Recommended For New Designs
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