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參數資料
| 型號： | U634H256CD1C25 |
| 英文描述： | NVRAM (EEPROM Based) |
| 中文描述： | NVRAM中（EEPROM的基礎） |
| 文件頁數： | 9/14頁 |
| 文件大小： | 239K |
| 代理商： | U634H256CD1C25 |
9
December 12, 1997
U634H256
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u: If the chip enable pulse width is less then t
a(E)
(see READ cycle) but greater than or equal to t
w(E)SR
, then the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
v:
W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW
throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines whether the U634H256 performs a STORE
or RECALL.
w: E must be used to clock in the address sequence for the software controlled STORE and RECALL cycles.
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Ai
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DQi
Output
t
cR
t
w(E)SR
ADDRESS 1
VALID
SOFTWARE CONTROLLED STORE/RECALL CYCLE
t, u, v, w
(E = HIGH after STORE initiation)
ADDRESS 6
t
cR
29
29
t
h(A)SR
35
34
t
su(A)SR
33
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Output
t
cR
t
w(E)SR
ADDRESS 1
VALID
VALID
ADDRESS 6
t
d(E)S
/ t
d(E)R
31
32
/
29
t
h(A)SR
35
34
t
su(A)SR
33
t
dis(E)SR
30
t
h(A)SR
35
t
su(A)SR
33
t
w(E)SR
t
h(A)SR
35
34
t
su(A)SR
33
5
t
dis(E)
SOFTWARE CONTROLLED STORE/RECALL CYCLE
t, u, v, w
(E = LOW after STORE initiation)
t
dis(E)SR
30
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VALID
High Impedance
High Impedance
t
d(E)S
/ t
d(E)R
31
32
/
相關PDF資料 |
PDF描述 |
|---|---|
| U634H256CD1C35 | NVRAM (EEPROM Based) |
| U634H256CD1C45 | NVRAM (EEPROM Based) |
| U634H256CD1K25 | NVRAM (EEPROM Based) |
| U634H256CD1K35 | NVRAM (EEPROM Based) |
| U634H256CD1K45 | NVRAM (EEPROM Based) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| U634H256CD1C35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
| U634H256CD1C45 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
| U634H256CD1K25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
| U634H256CD1K35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
| U634H256CD1K45 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:NVRAM (EEPROM Based) |
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