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參數(shù)資料
| 型號： | U635H64SK35 |
| 英文描述： | NVRAM (EEPROM Based) |
| 中文描述： | NVRAM中（EEPROM的基礎(chǔ)） |
| 文件頁數(shù)： | 8/13頁 |
| 文件大小： | 132K |
| 代理商： | U635H64SK35 |
8
November 01, 2001
U635H16
PowerStore
and automatic Power Up RECALL
o:
p:
q:
r:
The software sequence is clocked with E controlled READs.
Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
Note that STORE cycles (but not RECALL) are aborted by V
< V
(STORE inhibit).
An automatic RECALL also takes place at power up, starting when V
CC
exceeds V
SWITCH
and takes t
RESTORE
. V
CC
must not drop below
V
SWITCH
once it has been exceeded for the RECALL to function properly.
Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence.
If the Chip Enable Pulse Width is less than t
a(E)
(see Read Cycle) but greater than or equal t
w(E)SR
, than the data may not be valid at
the end of the low pulse, however the STORE or RECALL will still be initiated.
s:
t:
No.
Software Controlled STORE/
RECALL Cycle
k, o
Symbol
25
35
45
Unit
Alt.
IEC
Min. Max. Min. Max. Min. Max.
27
STORE/RECALL Initiation Time
t
AVAV
t
cR
25
35
45
ns
28
Chip Enable to Output Inactive
p
t
ELQZ
t
dis(E)SR
600
600
600
ns
29
STORE Cycle Time
q
t
ELQXS
t
d(E)S
10
10
10
ms
30
RECALL Cycle Time
r
t
ELQXR
t
d(E)R
20
20
20
μ
s
31
Address Setup to Chip Enable
s
t
AVELN
t
su(A)SR
0
0
0
ns
32
Chip Enable Pulse Width
s, t
t
ELEHN
t
w(E)SR
20
25
35
ns
33
Chip Disable to Address Change
s
t
EHAXN
t
h(A)SR
0
0
0
ns
V
CC
5.0 V
V
SWITCH
t
PowerStore
Power Up
RECALL
W
DQi
POWER UP
RECALL
BROWN OUT
NO STORE
t
RESTORE
t
RESTORE
BROWN OUT
PowerStore
(NO SRAM WRITES)
(24)
(24)
t
PDSTOREp
(25)
t
DELAY
(26)
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