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參數資料
| 型號： | U637H256DC25G1 |
| 英文描述： | CapStore 32K x 8 nvSRAM |
| 中文描述： | CapStore 32K的× 8非易失 |
| 文件頁數： | 5/14頁 |
| 文件大小： | 158K |
| 代理商： | U637H256DC25G1 |
U637H256
5
August 15, 2006
STK Control #ML0056
Rev 1.1
Read Cycle 1: Ai-controlled (during Read cycle: E = G = V
IL
, W = V
IH
)
f
Read Cycle 2: G-, E-controlled (during Read cycle: W = V
IH
)
g
No.
Switching Characteristics
Write Cycle
Symbol
Min.
Max.
Unit
Alt. #1
Alt. #2
IEC
12
Write Cycle Time
t
AVAV
t
AVAV
t
cW
25
ns
13
Write Pulse Width
t
WLWH
t
w(W)
20
ns
14
Write Pulse Width Setup Time
t
WLEH
t
su(W)
20
ns
15
Address Setup Time
t
AVWL
t
AVEL
t
su(A)
0
ns
16
Address Valid to End of Write
t
AVWH
t
AVEH
t
su(A-WH)
20
ns
17
Chip Enable Setup Time
t
ELWH
t
su(E)
20
ns
18
Chip Enable to End of Write
t
ELEH
t
w(E)
20
ns
19
Data Setup Time to End of Write
t
DVWH
t
DVEH
t
su(D)
10
ns
20
Data Hold Time after End of Write
t
WHDX
t
EHDX
t
h(D)
0
ns
21
Address Hold after End of Write
t
WHAX
t
EHAX
t
h(A)
0
ns
22
W LOW to Output in High-Z
h, i
t
WLQZ
t
dis(W)
10
ns
23
W HIGH to Output in Low-Z
t
WHQX
t
en(W)
5
ns
t
a(A)
Previous Data Valid
Output Data Valid
t
cR
Address Valid
t
v(A)
Ai
DQi
Output
(1)
(2)
(9)
Ai
E
G
t
dis(E)
t
cR
t
a(E)
t
en(E)
t
en(G)
t
a(G)
t
dis(G)
Address Valid
t
a(A)
(2)
Output Data Valid
I
CC
ACTIVE
STANDBY
t
PD
t
PU
(1)
(3)
(4)
(5)
(7)
(6)
(8)
(10)
(11)
High Impedance
DQi
Output
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