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參數資料
| 型號： | U7006B |
| 英文描述： | U7006B [Updated 7/03. 12 Pages] DECT SiGe Front-end IC with High PAE |
| 中文描述： | U7006B [更新7月3日。 12頁]無繩硅鍺前端高PAE的集成電路 |
| 文件頁數： | 4/12頁 |
| 文件大小： | 341K |
| 代理商： | U7006B |
4
U7006B
4714A–DECT–07/03
Saturated output power
TX, referred to pins 6, 7, 8
V
S
= 3.6 V
TX, pin 11
P
sat
26.5
dBm
Input matching
(2)
Output matching
(2)
VSWRin
< 2:1
TX, pins 6, 7, 8
VSWRout
< 2:1
Harmonics at P 1dB
TX, pins 6, 7, 8
2 fo
3 fo
-30
dBc
Maximum input power
Pin 11
P
inPA
10
dBm
Stability (non harmonic emission)
TX, pin 10
P
in
= 2 dBm, V
RAMP
= 2 V
VSWRout < 10:1 (all phases)
-60
dBc
T/R Switch Driver (Currently Programmed by External Resistor from R_SWITCH to GND)
Switch-out current output
Standby, pin 2
I
S_O_standby
I
S_O_RX
I
S_O_100
I
S_O_1k2
I
S_O_33k
2
μA
RX
2
μA
TX at 100
1
mA
TX at 1.2 k
3
mA
TX at 33 k
10
mA
Low-noise Amplifier
(3)
Supply voltage
All, pin 12
V
S
I
S
2.7
3.6
4.6
V
Supply current
RX
8
mA
Supply current
(LNA and control logic)
TX (control logic active), pin 12
I
S
300
μA
Standby current
Standby, pin 12
I
S
f
1
10
μA
Frequency range
RX
1.88
1.94
GHz
Power gain
RX, pin 4 to pin 14
Gp
17
19
dB
Noise figure
RX
NF
1.8
2.0
dB
Gain compression
RX, refer to pin 14
P1dB
-7
dBm
3rd-order input interception point
RX
IIP3
-15
dBm
Input matching
RX
VSWRin
< 2:1
Output matching
Logic Input Levels (RX_ON, PU)
RX
VSWRin
< 2:1
High input level
= 1, pins 5 and 16
V
iH
V
iL
I
iH
I
iL
2.4
V
S
0.5
V
Low input level
= 0
0
V
High input current
= 1
40
μA
Low input current
Notes:
= 0
0
μA
Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): V
S
= 3 V, T
amb
= 25°C, CW mode
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
1. Power amplifier shall be unconditionally stable, maximum duty cycle 50%, maximum load mismatch and duration: TBD
2. With external matching network (see Figure 13 )
3. Low-noise amplifier shall be unconditionally stable
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相關代理商/技術參數 |
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| U7006B-MLB | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:DECT SiGe Front End IC with High PAE |
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