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參數(shù)資料
| 型號： | U834BS-FP |
| 英文描述： | 3-GHz Frequency Divider |
| 中文描述： | 3 - GHz的分頻器 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大小： | 117K |
| 代理商： | U834BS-FP |
U832BS / U834BS
TELEFUNKEN Semiconductors
Rev. A2, 27-Jan-97
5 (6)
Application
Master-Slave-D-Flip-Flops (MS-D-FF’s) can be used for
frequency division by feeding back the inverted output to
the data input. Typical for this kind of dividers is a free–
running oscillation of the first divider stage. Here, the
input sensitivity of the circuit is minimal (see data sheet
page 5: input sensitivity vs. frequency). An oscillation
frequency of, e.g., 3.5 GHz (related to the input) will
result in an output the part number of frequency of
3.5 GHz: 4 = 875 MHz. To indicate this, TEMIC’s self-
oscillating frequency dividers are ending with “S”
(U834BS-AFP). This oscillation is often used for the
quality control of ICs: the higher the frequency, the better
the performance. It occurs only if the offset voltage of the
input transistor pair is below a certain limit.
On the other hand, if this oscillation causes problems,
e.g., in frequency counters, an external offset may be
added. This can simply be done by connecting an ohmic
resistor from Pin 3 (RF input) to ground. Using a value of
R
3
= 47 k will stop self oscillation without degrading
the input sensitivity markly. Smaller values will decrease
the sensitivity especially at higher frequencies.
1
U832BS
U834BS
2
3
4
8
7
6
5
< 50 k
R
3
100 pF
RF
input
100 pF
470 pF
470 pF
1
U891BS
U893BSE
2
3
4
8
7
6
5
RF
output
1 nF
V
Batt
13291
Figure 5.
Package Information
Package SO8
Dimensions in mm
13034
technical drawings
5.00
4.85
0.4
1.27
3.81
1.4
0.25
0.10
5.2
4.8
3.7
3.8
6.15
5.85
0.2
8
5
8
5
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