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參數(shù)資料
| 型號： | UA1 |
| 英文描述： | Rail-to-rail high output current dual operational amplifier |
| 中文描述： | UA1 [更新12/01。 8頁]超低價的FPGA轉換 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 135K |
| 代理商： | UA1 |
Rev. B – 05-Dec-01
1
Features
High performance ULC family suitable for large-sized CPLDs and FPGAs
Conversion to 1,000,000 gates
Pin counts to over 976 pins
Any pin–out matched due to limited number of dedicated pads
Full range of packages: DIP, SOIC, LCC/PLCC, PQFP/TQFP, BGA, PGA/PPGA
Low quiescent current: 0.3 nA/gate
Available in commercial and industrial grades
0.35 μm Drawn CMOS, 3 and 4 Metal Layers
Library Optimised for Synthesis, Floor Plan & Automatic Test Pattern
Generation (ATPG)
High Speed Performances:
– 150 ps Typical Gate Delay @3.3V
– Typical 600 MHz Toggle Frequency @3.3V
– Typical 360 MHz Toggle Frequency @2.5V
High System Frequency Skew Control:
– Clock Tree Synthesis Software
Low Power Consumption:
– 0.25
μ
W/Gate/ MHz @3.3V
– 0.18
μW
/Gate/ MHz @2.5V
Power on Reset
Standard 2, 4, 6, 8,10, 12 and 18mA I/Os
CMOS/TTL/PCI Interface
ESD (2 kV) and Latch-up Protected I/O
High Noise & EMC Immunity:
– I/O with Slew Rate Control
– Internal Decoupling
– Signal Filtering between Periphery & Core
Description
The UA1 series of ULCs is well suited for conversion of large sized CPLDs and
FPGAs. Devices are implemented in high–performance CMOS technology with
0.35μm (drawn) channel lengths, and are capable of supporting flip–flop toggle rates
of 200 MHz at 3.3V and 180 MHz at 2.5V, and input to output delays as fast as 150ps
at 3.3V. The architecture of the UA1 series allows for efficient conversion of many PLD
architecture and FPGA device types with higher IO count. A compact RAM cell, along
with the large number of available gates allows the implementation of RAM in FPGA
architectures that support this feature, as well as JTAG boundary–scan and scan–
path testing.
Conversion to the UA1 series of ULC can provide a significant reduction in operating
power when compared to the original PLD or FPGA. This is especially true when
compared to many PLD and CPLD architecture devices, which typically consume
100mA or more even when not being clocked. The UA1 series has a very low
standby consumption of 0.3nA/gate typically commercial temperature, which would
yield a standby current of 42μA on a 144,000 gates design. Operating consumption is
a strict function of clock frequency, which typically results in a power reduction of 50%
to 90% depending on the device being compared.
The UA1 series provides several options for output buffers, including a variety of drive
levels up to 18mA. Schmitt trigger inputs are also an option. A number of techniques
are used for improved noise immunity and reduced EMC emissions, including: several
independent power supply busses and internal decoupling for isolation; slew rate lim-
ited outputs are also available if required. The UA1 series is designed to allow
conversion of high performance 3.3V devices as well as 2.5V devices.
0.35
μm
ULC
Series
UA1
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