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參數(shù)資料
| 型號(hào)： | UART_AU1000_REV002 |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-bit MCU for automotive with 16 to 60 Kbyte Flash, ADC, CSS, 5 timers, SPI, SCI, I2C interface |
| 中文描述： | 編寫具有了AMD Alchemy的UART設(shè)備驅(qū)動(dòng)程序？解決方案Au1000？處理器？ |
| 文件頁(yè)數(shù)： | 3/4頁(yè) |
| 文件大小： | 32K |
| 代理商： | UART_AU1000_REV002 |
Application Note
3
Writing a UART Device Driver for the Au1000 Processor
Rev. 002
September 2001
Introduction
The Au1000 processor integrates four Universal Asynchronous Receiver/Transmitters, UART.
Each of the four UARTs is very similar to the personal computer industry standard NS16550
UART[1]. This document outlines the differences in order to assist the device driver developer.
When starting the development of the Au1000 UART device driver, it is best to start with an existing
NS16550 driver, which virtually every operating system supports. After reading the remainder of this
document, the developer can then decide to make modifications to the existing driver, or change the
driver into a UART driver specific to the Au1000 processor.
Register Set Differences
The Au1000 UART register set is very similar to the NS16550. The differences are depicted in the
table below.
The register set differences are:
Each Au1000 UART register has a unique address.
Each Au1000 UART is 32-bits wide. The 8-bit value is in the least-significant byte of the register.
The Au1000 processor does not implement the NS16550 scratch register, SCR.
NS16550
Au1000 Processor
Register Name
Offset
Register Name
Offset
RBR
0 (rd)
uart_rxdata
0 (0x0000)
THR
0 (wr)
uart_txdata
1 (0x0004)
IER
1 (r/w)
uart_inten
2 (0x0008)
IIR
2 (rd)
uart_intcause
3 (0x000C)
FCR
2 (wr)
uart_fifoctrl
4 (0x0010)
LCR
3 (r/w)
uart_linectrl
5 (0x0014)
MCR
4 (r/w)
uart_mdmctrl
6 (0x0018)
LSR
5 (r/w)
uart_linestat
7 (0x001C)
MSR
6 (r/w)
uart_mdmstat
8 (0x0020)
SCR
7 (r/w)
DLL/DLM
0/1 (DLAB=1)
uart_clkdiv
10 (0x0028)
uart_enable
(0x0100)
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