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參數(shù)資料
| 型號(hào)： | UC2727LP |
| 英文描述： | SINGLE CHANNEL HIGH SIDE SOLID STATE RELAY |
| 中文描述： | 單外設(shè)驅(qū)動(dòng) |
| 文件頁(yè)數(shù)： | 5/7頁(yè) |
| 文件大小： | 414K |
| 代理商： | UC2727LP |
UC1727
UC2727
UC3727
APPLICATION INFORMATION
(cont.)
Figure 4.
Rising Edge Waveform
Figure 5.
Transient Desaturation Response
GATE DRIVE WAVEFORM
The rising edge of OUT can be programmed for a two
step sequence as shown in Figure 4. The plateau voltage
is programmed by a resistive divider from V
CC
to COM
applied at CLAMP. CLAMP must be bypassed to COM.
The plateau voltage is approximately OUT = CLAMP. The
plateau time is set by a resistor from TRC to V
CC
and a
capacitor to COM as:
Tp
=
RCln
R
7.6k
R
12.4k
.
TRC also programs a blanking time during which the chip
ignores the desaturation comparator. The blanking time
is:
Tb = Tp + 0.4RC.
In the event that desaturation is detected outside the
blanking interval, OUT will be driven back to the CLAMP
plateau for a fault time set by a resistor from FRC to V
CC
and a capacitor to COM as:
Tf
=
RCln
R
7.6k
R
12.4k
.
If the event is transient, OUT will return high at the end of
Tf as shown in Figure 5. During Tf, FRPLY is open. After
Tf, FRPLY is connected to COM.
Desaturation shown in Figure 6 that persists longer than
Tf will cause OUT to be driven low. The chip will not ac-
cept a command to drive OUT high for a delay period of
Td = 0.4RC
FRPLY will be open during this entire period.
Figure 2.
Input Waveform
Figure 3.
Output Pulsing Caused By Transformer Ringing
5
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