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參數資料
| 型號： | UC3910DTR |
| 英文描述： | VERY LOW QUIESCENT CURRENT DUAL VOLTAGE REGULATOR |
| 中文描述： | D / A轉換 |
| 文件頁數： | 3/6頁 |
| 文件大小： | 247K |
| 代理商： | UC3910DTR |
UC1910
UC2910
UC3910
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Monitor Circuitry (Note 2) (cont.)
VSENSE OVP Threshold Voltage
Code 0, Ratio = 0.45
Code 0, Ratio = 0.9
Code 15, Ratio = 0.45
Code 15, Ratio = 0.9
Code 0, Ratio = 0.9
Code 15, Ratio = 0.45
Code 0, Ratio = 0.9
Code 15, Ratio = 0.45
OV, UV, OVP Comparators
OV, UV Comparators
OVP Comparator
3.937
4.41
2.235
2.505
70
15
160
40
0
4.025
4.55
2.3
2.6
88
25
218
62
4.113
4.69
2.365
2.695
120
40
300
85
5
5
5
V
V
V
V
OV, UV Comparator Hysteresis
mV
mV
mV
mV
V
μ
s
μ
s
OVP Comparator Hysteresis
Input Common Mode Range
Propagation Delay
PWRGOOD, OVP, OVPB Outputs
PWRGOOD Voltage Low
OVP Sourcing Current
OVPB Voltage Low
I
PWRGOOD
= 10mA
V
OVP
= 1.4V
I
OVPB
= 1mA
0.4
V
65
mA
V
0.4
ELECTRICAL CHARACTERISTICS (cont.)
Unless otherwise specified, VCC = 12V, VSENSE = 3.5V, V
OVTH/UVTH
=
1.26V, V
D0
= V
D1
= V
D2
= V
D3
= 0V, 0°C < T
A
< 70°C for the UC3910, –25°C < T
A
< 80°C for the UC2910, –55°C < T
A
< 125°C for
the UC1910 T
A
= T
J
.
D0-D3 (DAC Digital Input Control Codes):
These are
the DAC digital input control codes, with D0 repre-
senting the least significant bit (LSB) and D3, the most
significant bit (MSB) (See Table 1). A bit is set low by
being connected to GND; a bit is set high by floating it,
or connecting it to a 3V to 5V voltage source. Each con-
trol pin is pulled up to approximately 4.8V by an internal
40
μ
A current source.
DACBUF (Buffered DACOUT Voltage):
This pin pro-
vides a buffered version of the DACOUT voltage to al-
low external programming of the OV/UV thresholds (see
OVTH/UVTH below).
DACOUT (Digital-to-Analog Converter Output Volt-
age):
This pin is the output of the 4-bit digital to analog
(DAC) converter. Setting all input control codes low pro-
duces 3.5V at DACOUT; setting all codes high pro-
duces 2.0V at DACOUT. The LSB step size (i.e.
resolution) is 100mV (See Table 1). The DACOUT
source impedance is typically 3k
and must therefore
drive a high impedance input. Bypass DACOUT at the
driven input with a 0.01
μ
F, low ESR, low ESL capacitor
for best circuit noise immunity.
GND (Signal Ground):
All voltages are measured with
respect to GND. The two GND pins are connected to-
gether internally but should also be connected exter-
nally using a short PC board trace. Bypass capacitors
on the VCC and VREF pins should be connected di-
rectly to the ground plane near one of the signal ground
PIN DESCRIPTIONS
Note 1: "Line, Load" implies that the parameter is tested at all combinations of the conditions:
10.8V < VCC < 13.2V –2mA < I
VREF
< 0mA.
Note 2: These are the actual voltages on VSENSE which will cause the OVPB and PWRGOOD outputs to switch, assuming the
DACOUT voltage is perfect. These limits apply for 0°C < T
A
< 70°C.
Note 3: "Code 0" means pins D0 - D4 are all low; "Code 15" means they are all floating or high (See Table 1). "Ratio" is the divider
ratio of the resistor string between DACBUF and OVTH/UVTH (See Figure 1).
Decimal
Code
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
D3
D2
D1
D0
DACOUT
Voltage
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Table 1. Programming the DACOUT Voltage
3
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