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參數資料
| 型號： | UCC1913D |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Very low drop voltage regulators with inhibit |
| 中文描述： | 模擬IC |
| 文件頁數： | 4/9頁 |
| 文件大小： | 158K |
| 代理商： | UCC1913D |
4
UCC1913
UCC2913
UCC3913
8
5
6
4
OVERCURRENT
COMPARATOR
R
PL
PL
R
S
SENSE
+
VSS
VSS
INPUT VOLTAGE
OUTPUT
LOAD
V
DD
I1
36
μ
A
S
Q
Q
R
H=CLOSE
I2
1
μ
A
I3
1mA
+
SENSE
IMAX
H=CLOSE
0.5V
2.5V
C
T
VSS
TO OUTPUT
DRIVE
H=OFF
OVERLOAD COMPARATOR
CT
FAULT TIMING CIRCUITRY
0.2V
5.0V
50mV
APPLICATION INFORMATION
Figure 1. Fault timing circuitry for the UCC1913, including power limit overload.
Figure 1 shows the detailed circuitry for the fault timing
function of the UCC1913. For the time being, we will dis-
cuss a typical fault mode, therefore, the overload com-
parator, and current source I3 does not work into the
operation. Once the voltage across the current sense re-
sistor, R
S
, exceeds 50mV, a fault has occurred. This
causes the timing capacitor to charge with a combination
of 36
μ
A plus the current from the power limiting amplifier.
The PL amplifier is designed to only source current into
the CT pin and to begin sourcing current once the volt-
age across the output FET exceeds 5V. The current I
PL
is related to the voltage across the FET with the following
expression:
V
V
R
PL
I
PL
FET
=
5
Where V
FET
is the voltage across the NMOS pass de-
vice.
Later it will be shown how this feature will limit average
power dissipation in the pass device. Note that under a
condition where the output current is more than the fault
level, but less than the max level, V
OUT
~ VSS (input
voltage), I
PL
= 0, the CT charging current is 36
μ
A.
During a fault, CT will charge at a rate determined by the
internal charging current and the external timing capaci-
tor. Once CT charges to 2.5V, the fault comparator
switches and sets the fault latch. Setting of the fault latch
causes both the output to switch off and the charging
switch to open. CT must now discharge with the 1
μ
A cur-
rent source, I2, until 0.5V is reached. Once the voltage at
CT reaches 0.5V, the fault latch resets, which re-enables
the output and allows the fault circuitry to regain control
of the charging switch. If a fault is still present, the fault
comparator will close the charging switch causing the cy-
cle to begin. Under a constant fault, the duty cycle is
given by:
A
I
A
PL
+
36
μ
DutyCycle
=
1
μ
Average power dissipation in the pass element is given
by:
P
V
IMAX
A
36
I
A
FET avg
(
FET
PL
)
=
+
1
μ
μ
where V
FET
>> 5V I
PL
can be approximated as :V
R
FET
PL
and where I
PL
>>36
μ
A, the duty cycle can be approxi-
mated as :
UDG-99004
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