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參數資料
| 型號： | UCC1913DTR |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數： | 5/9頁 |
| 文件大小： | 158K |
| 代理商： | UCC1913DTR |
5
UCC1913
UCC2913
UCC3913
I
OUT
I
MAX
I
FAULT
Io(nom)
0A
V
CT
2.5V
0.5V
0V
0V
V
OUT
VSS
t
0
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
t
t
Output
Current
C
T
Voltage
(w/respecttoVSS)
Output
Voltage
(w/respecttoGND)
APPLICATION INFORMATION (cont.)
Figure 2. Typical timing diagram.
t0: safe condition – output current is nominal, output
voltage is at the negative rail, VSS.
t1: fault control reached – output current rises above
the programmed fault value, CT begins to charge at
36
μ
A.
t2: max current reached – output current reaches the
programmed maximum level and becomes a con-
stant current with value I
MAX
.
t3: fault occurs – CT has charged to 2.5V, fault output
goes high, the FET turns off allowing no output cur-
rent to flow, V
OUT
floats up to ground.
t4: retry – CT has discharged to 0.5V, but fault current
is still exceeded, CT begins charging again, FET is
on, V
OUT
pulled down to VSS.
t5:
t5 = t3: illustrates 3%duty cycle.
t6:
t6 = t4
t7: output short circuit - if V
OUT
is short circuited to
ground, CT charges at a higher rate depending
upon the values for VSS and R
PL
.
t8: fault occurs – output is still short circuited, but the
occurrence of a fault turns the FET off so no current
is conducted.
t9: t9 = t4; output short circuit released, still in fault
mode.
t10: t10 = t0; fault released, safe condition – return to
normal operaton of the circuit breaker.
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