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參數資料
| 型號： | UCC1913N |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Very low drop voltage regulators with inhibit |
| 中文描述： | 模擬IC |
| 文件頁數： | 3/9頁 |
| 文件大小： | 158K |
| 代理商： | UCC1913N |
3
UCC1913
UCC2913
UCC3913
ELECTRICAL CHARACTERISTICS:
Unless otherwise stated these specifications apply for T
A
= –55°C to +125°C for
UCC1913; –40°C to +85°C for UCC2913; 0°C to +70°C for UCC3913; I
VDD
= 2mA, CT = 4.7pF, T
A
= T
J
PARAMETER
TEST CONDITIONS
Power Limiting Section
V
SENSE
Regulator Voltage
I
PL
= 64 A
Duty Cycle Control
I
PL
= 64
μ
A
I
PL
= 1mA
Overload Section
Delay to Output
(Note 1)
Output Sink Current
V
SENSE
= V
IMAX
= 300mV
Threshold
Relative to IMAX
MIN
TYP
MAX
UNITS
4.35
0.6
0.045
4.85
1.2
0.1
5.35
1.7
0.17
V
%
%
300
100
200
500
ns
mA
mV
40
140
260
Note 1: Guaranteed by design. Not 100% tested in production.
CT:
A capacitor is connected to this pin in order to set the
maximum fault time. The maximum fault time must be
more than the time to charge external load capacitance.
The maximum fault time is defined as:
(
)
T
I
CH
CT
FAULT
=
2
where
I
A I
CH
PL
=
36
μ
,
and I
PL
is the current into the power limit pin. Once the
fault time is reached the output will shutdown for a time
given by:
T
CT
SD
=
IMAX
: This pin programs the maximum allowable sour-
cing current. Since VDD is a regulated voltage, a voltage
divider can be derived from VDD to generate the pro-
gram level for the IMAX pin. The current level at which
the output appears as a current source is equal to the
voltage on the IMAX pin over the current sense resistor.
If desired, a controlled current startup can be pro-
grammed with a capacitor on the imax pin, and a pro-
grammed start delay can be achieved by driving the
shutdown with an open collector/drain device into an RC
network.
OUT
: Output drive to the MOSFET pass element.
PL
: This feature ensures that the average MOSFET
power dissipation is controlled. A resistor is connected
from this pin to the drain of the NMOS pass element.
When the voltage across the NMOS exceeds 5V, current
will flow into the PL pin which adds to the fault timer
charge current, reducing the duty cycle from the 3%
level. When I
PL
>>36
μ
A then the average MOSFET
power dissipation is given by:
P
IMAX
R
FET avg
(
PL
)
=
6
SENSE
: Input voltage from the current sense resistor.
When there is greater than 50mV across this pin with re-
spect to VSS, then a fault is sensed, and CT starts to
charge.
SD/FLT
: This pin provides fault output indication and
shutdown control. Interface into and out of this pin is usu-
ally performed through level shift transistors. When 20
μ
A
is sourced into this pin, shutdown drives high causing the
output to disable the NMOS pass device. When opened,
and under a non-fault condition, the SD/FLT pin will pull
to a low state. When a fault is detected by the fault timer,
or undervoltage lockout, this pin will drive to a high state,
indicating the output FET is off.
VDD
: Current driven with a resistor to a voltage at least
10V more positive than VSS. Typically a resistor is con-
nected to ground. The 10V shunt regulator clamps VDD
at 10V above the VSS pin, and is also used as an output
reference to program the maximum allowable sourcing
current.
VSS
: Ground reference for the IC and the most negative
voltage available.
PIN DESCRIPTIONS
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